Other for TSMC
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- 3nm
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INNOLINK-B PHY
- Support both Die2Die and Chip2Chip application
- GDDR6 like interface with IO voltage is core power supply (0.8V for TSMC 12nm)
- 24Gbps for maximum IO speed
- Default 16bit DQ Tx+ 16bit DQ Rx per module, module number can be 1/2/4/8/16 or more
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IPTD2D-A PHY and Controller
- Supports CoWoSTM, INFOTM and EMIBTM package technologies
- Supports any speed ranging from 2Gbps to 16Gbps, achieving the best balance between total bandwidth and power consumption
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TSMC CLN3FFE GLink 2.3LL Die-to-Die PHY
- 56 full-duplex lanes per slice
- 6-Slice/2-Slice PMA included in the analog hard macro
- Lane repair