INNOLINK-B PHY

Overview

Innosilicon can provide different Die2Die solution for customer depend on package type, Following is Innosilicon Die2Die IP family:
Innolink-A, Serdes base, up to 32/56Gbps/pair, long reach, chip to chip or board to board connection.
Innolink-B, gddr like, single ended, up to 24Gbps/pin, typical MCM or short PCB application, bump pitch 100um~180um.
Innolink-C, gddr and lpddr5 like, optimized for silicon interposer, super small IO and 0.4V IO voltage, max 24Gbps/pin, bump pitch 40um~100um.
This document contains specifications of INNOLINK-B, Innosilicon can provide only PHY solution, and we can also provide PHY + Controller solution, this data sheet is for PHY solution with DFI like interface. Innolink PHY is full harden IP, Innolink Controller is soft IP.
INNOLINK-B is designed to perform high speed data communication between dies or chips. The physical implementation methodology of INNOLINK-B is a DDR-like interface, which use single ended signal for IO interface, forward clock is used for Rx data sampling.
In this document, the DDR-like INNOLINK-B is adopted, Innolink-B use 16bit Tx DQs +16bit Rx DQs per module , when each DQ runs at 24Gbps and configured with two modules (32bit Tx + 32bit Rx), total bandwidth will be 768Gbps for TX and 768Gbps for RX. Innolink-B can be configured to 1/2/4/8/16/32 modules, and this data sheet is an example of 1 module.
Innolink can be easily integrated with innolink controller, and IO input/output direction can be software defined.

Key Features

Support both Die2Die and Chip2Chip application
GDDR6 like interface with IO voltage is core power supply (0.8V for TSMC 12nm)
24Gbps for maximum IO speed
Default 16bit DQ Tx+ 16bit DQ Rx per module, module number can be 1/2/4/8/16 or more
Burst data, forward clock, no CDR
Support organic substrate or short PCB
Minimum bump pitch is 100um
Support Driver strength and ODT strength adjustable
IO is bi-directional, software can define IO direction
Support data remap for easy connection
Support PHY independent handshake and training
Support per-bit delay and vref 2D training
Support on die eye opening read out (on die scope)
Automatic VT tracking and compensation
DFI like interface to core logic
BIST logic integrated
PLL integrated to generate high speed clocks
Sideband interface for low speed communication between both PHYs
Support DBI for low power
PHY independent Tx and Rx training,Support per bit training
All signal IOs are bidirectional, software can define input or output

Benefits

Available in any 40nm or below technology nodes
Significantly lower cost, shorter time to market, lower supply risks for OEMs and simpler architectural partitioning than the monolithic silicon integration
Offers leading performance, power, and area per terabit
Flexible configuration with support for silicon interposer, package substrate and PCB options
Customizable synthesis for any FPGAs and ASICs
Full support from IP delivery to production

Applications

High performance computing (HPC) applications
Next-generation data center
Networking
5G communication
Artificial intelligence / machine learning (AI/ML) applications

Deliverables

Databook and physical implementation guides
Netlist (Spice format for LVS)
Library Exchange Format (LEF)
Verilog Models
GDSII to Foundry IP Merge
Module integration guidelines
Silicon validation report (when available)
Evaluation board (when available)

Technical Specifications

Foundry, Node

TSMC12/6/5/4/3nm, SMIC 14nm, GF 12nm, Samsung14/10/5/4nm, HLMC 28nm

GLOBALFOUNDRIES

In Production: 12nm
Silicon Proven: 12nm

SMIC

In Production: 14nm
Silicon Proven: 14nm

Samsung

In Production: 4nm , 5nm , 10nm , 14nm
Pre-Silicon: 14nm
Silicon Proven: 4nm , 5nm , 10nm , 14nm

TSMC

In Production: 3nm , 4nm , 5nm , 6nm , 12nm
Silicon Proven: 3nm , 4nm , 5nm , 6nm , 12nm

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