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PCI Express Phy IP for SMIC

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Compare 16 PCI Express Phy IP for SMIC from 4 vendors (1 - 10)
  • PCIe 2.0 PHY, SMIC 28HKMG18 x1, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • PCIe L1 substate power management
    • Supports power gating and power island
    Block Diagram -- PCIe 2.0 PHY, SMIC 28HKMG18 x1, North/South (vertical) poly orientation
  • PCIe 2.0 PHY in SMIC (40nm, 28nm)
    • Physical coding sublayer (PCS) block with PIPE interface
    • Supports PCIe power management features, including L1 substate
    • Power gating for lowest standby power
    • Low active power using voltage mode TX with under drive supply options
  • PCIe4/3/2/1 PHY & Controller
    • Reference Clock:
    • Internal PLL:
    • Data Transmit:
    • Data Receive:
  • SGMII PHY
    • General:
    • Interface:
    • PMA-TX:
    • PMA-RX:
  • PCIe5.0 PHY & Controller
    • Fully compliant with PCI Express Base Specification Revision 5.0
    • Fully compliant with PIPE Specifications Revision 4.4.1
    • Support Root Complex and Endpoint Mode
    • Support Gen1 (2.5Gbps), Gen2 (5Gbps), Gen3 (8Gbps), Gen4 (16Gbps), Gen5 (32Gbps)
  • PCIe4.0 PHY
    • Reference Clock:
    • Internal PLL:
    • Data Transmit:
    • Data Receive:
  • PCIe4.0 Controller
    • Fully compliant with PCI Express Base Specification Revision 4.0.
    • Fully compliant with PIPE Specifications Revision 4.4.1.
    • Support Root Complex and Endpoint Mode.
    • Support Gen1 (2.5Gbps), Gen2 (5Gbps), Gen3 (8Gbps), Gen4 (16Gbps)
  • PCIe3.0 PHY
    • Reference Clock:
    • Internal PLL:
    • Data Transmit:
    • Data Receive:
  • PCIe3.0 Controller
    • Fully compliant with PCI Express Base Specification Revision 3.0.
    • Fully compliant with PIPE Specifications Revision 4.4.1
    • Support Root Complex and Endpoint Mode.
    • Support Gen1 (2.5Gbps), Gen2 (5Gbps), Gen3 (8Gbps)
  • PCIe2.0 PHY & Controller
    • Reference Clock:
    • Internal PLL:
    • Data Transmit:
    • Data Receive:
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