Interconnect IP for Silterra
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Interconnect IP
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10
Interconnect IP
for Silterra
from 3 vendors
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10)
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High voltage tolerant I/O
- Scalable robustness
- Area efficient
- low capacitance option
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I2C Master / Slave Controller w/FIFO (APB Bus)
- I2C Master / Slave with Parameterized FIFO:
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I2C Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)
- I2C Master / Slave with Parameterized FIFO:
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I2C Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)
- I2C Master / Slave with Parameterized FIFO:
- Targets embedded processors with high performance algorithm requirements, by independently controlling the Transmit or Receive of bytes of information:
- Small VLSI footprint
- Master Controller Modes:
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I2C Master Controller w/FIFO (AXI & AXI-Lite Bus)
- I2C Master only with Parameterized FIFO:
- Targets embedded processors with high performance algorithm requirements, by independently controlling the Transmit or Receive of bytes of information:
- Small VLSI footprint
- Master Controller Modes:
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FPD-link, 30-Bit Color LVDS Receiver, 40-170Mhz (Full-HDTV @60Hz) LVDS SerDes 5:35 channel decompression with deskew capability
- Layout structure based on 1P6M, 1P7M, or 1P8M 0.13um Logic Salicide 1.2V/3.3V process.
- 1.2V/3.3V ±10% supply voltage, -40/+125°C
- Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
- Up to 5.6Gbps bandwidth (40 to 170Mhz pixel clock) ( supports Full HDTV 1080p )
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FPD-link, 30-Bit Color LVDS Receiver, 20-112Mhz (SVGA/WXGA/SXGA) LVDS SerDes 5:35 channel decompression
- Layout structure based on 1P6M, 1P7M, or 1P8M 0.13um Logic Salicide 1.2V/3.3V process.
- 1.2V/3.3V ±10% supply voltage, -40/+125°C
- Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
- Up to 3.15Gbps bandwidth (20 to 90Mhz pixel clock)
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Dual FPD-link, 30-Bit Color LVDS Transmitter, 40-170Mhz (Full-HD @120Hz) - with 2 independant links capability LVDS SerDes 70:10 channel compression
- 1P6M/1P7M/1P8M layout structure based on 0.13um Logic 1P8M Salicide 1.2V/3.3V process.
- 1.2V/3.3V ±10% supply voltage, -40/+125°C
- Complies with OpenLDI specification for digital display interfaces and LVDS IEEE Standard 1596.3-1996+ ANSI/TIA/EIA-644-A Specifications.
- Up to 11.9Gbps bandwidth (40 to 170Mhz pixel clock) per pixel channel (Full HD @ 120Hz)
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LVDS serdes 4:28 channel decompression RX 8-150Mhz
- FPD-LINK Receiver (also available in 30bits color 150Mhz dual channel)
- - 4:28 Data channel decompression up to 1050mb /lane
- - Wide Frequency Range: 8 - 150MHz suited for VGA,SVGA,XGA and SXGA
- - Narrow bus (10 lines) reduces cable size
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LVDS serdes 28:4 channel compression TX 20-170Mhz
- FPD-LINK Transmitter ( lowest pad count compare to other IP provider )
- 28:4 Data channel compression up to 1190Mbs/channel
- Wide Frequency Range: 20 - 170MHz (single channel) suited for VGA,SVGA,XGA and SXGA
- Narrow bus (10 lines) reduces cable size