Interconnect IP for Renesas
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7
Interconnect IP
for Renesas
from 3 vendors
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PCIe 3.0, 2.1, 1.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- Complies with the PCI Express® Base 3.0 Specification, rev.3.1
- Supports Endpoint, Root-Port, Dual-Role, Switch configurations
- Supports x16, x8, x4, x2, x1 at Gen3, Gen2, Gen1 speeds
- Implements one Virtual Channel
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PCIe 3.0, 2.1, 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with AMBA AXI User Interface
- PCIe Interface
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Low Power Multi-Rate SerDes
- Data rates of <200Mb/s to >8Gb/s
- Compatible with SGMII, SATA, FibreChannel, JESD 204, V-by-One
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I2C Master / Slave Controller w/FIFO (APB Bus)
- I2C Master / Slave with Parameterized FIFO:
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I2C Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)
- I2C Master / Slave with Parameterized FIFO:
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I2C Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)
- I2C Master / Slave with Parameterized FIFO:
- Targets embedded processors with high performance algorithm requirements, by independently controlling the Transmit or Receive of bytes of information:
- Small VLSI footprint
- Master Controller Modes:
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I2C Master Controller w/FIFO (AXI & AXI-Lite Bus)
- I2C Master only with Parameterized FIFO:
- Targets embedded processors with high performance algorithm requirements, by independently controlling the Transmit or Receive of bytes of information:
- Small VLSI footprint
- Master Controller Modes: