PSRAM PHY

Overview

The INNOSILICON DDR IPTM Mixed-Signal PSRAM PHY provides turnkey physical interface solutions for ICs requiring access to JEDEC compatible PSRAM devices. It is optimized for low power and high speed applications with robust timing and small silicon area. It supports APmemory UHS PSRAM components in the market. The PHY components contain PSRAM specialized functional and utility 2.5V IO devices, critical timing synchronization module (TSM), the low-jitter PLL, the TX and RX logic control for the PSRAM interface.
Note that all INNOSILICON PHY is pre-assembled with.lib, LEF and GDS so that it is very easy to integrate the PHY with any existing SoC floor plan. The DQ bus width can support 8 bit to match the PSRAM DQ interfaces. INNOSILICON is happy to pre-assemble each PHY for our customer so that integration becomes extremely easy.
The Innosilicon’s PSRAM PHY solution includes PSRAM controller and PHY. With configurable timing and driving strength parameters to interface to the wide variety of PSRAMs, the PHY is very flexible with advanced command capability to increase PSRAM operation efficiency.

Key Features

PSRAM modes & signaling, rates from 200Mbps up to 1600Mbps
x8 data path interface
2.5V I/O devices
Multiple drive strengths adjustable
Supports read and write timing adjustments with soft calibration
Low latency with programmable timings for secure data handling
Per bit deskew support
Supports point to point memory sub systems and multi-rank
Support ZQ calibration to calibrate driver output resistance and on-die termination resistance
PVT compensation and timing calibration for all corner reliability
At speed BIST, scan insertion
Various power-down modes for low power including self-refresh support
Low jitter with superior noise rejection
APB Port register access interface
Dual Row IO implementation and more
Implemented using 1.1V RVT&SVT core devices and 2.5V gate oxide IO devices
Supports both wire-bond and flip- chip packaging
Wire-bond speed is package limited

Benefits

Fully pre-assemble design, Drop-in hard macro to ease integration and speed time to market
Zero risk with robust ESD architecture
Maintains self-refresh I/O drive state during VDD power down
Extensive EDA tool support for various design automation flows
Optional /CE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external PSRAMs in self refresh mode
DFI compliant memory controller interface
Flexible pad ring configuration to adapt for various design and chip scenarios
Integration with other INNOSILICON interface IP
Takes full advantage of process power savings and speed capability
Best in class low noise design to ensure best timing margin and signal integrity
DFT functions to reduce test time and ensure high test coverage
Several programmable PHY operating modes through simple register interface
Per Bit De-skew to improve composite data eye during read cycles at high speed

Deliverables

Verilog models
LEF
Place-and-route abstracts
GDSII files
LVS netlists
Optional extracted HSPICE netlist for I/Os
Data book, Application notes
Silicon validation and ESD testing results
Optional PCB reference design and Package Electrical Model
DocumentationL: Documentation for the Innosilicon PHY will be delivered as part of the access package.

Technical Specifications

Foundry, Node

TSMC 40/22nm, GF 22nm

Maturity

Silicon Proven

Availability

Available

GLOBALFOUNDRIES

In Production: 22nm
Silicon Proven: 22nm

TSMC

In Production: 22nm , 40nm LP
Silicon Proven: 22nm , 40nm LP

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