Power Management IC - I3C Basic Interface IP

Overview

Power Management IC (PMIC) is designed for DDR5 RDIMM, DDR5 LRDIMM, DDR5 NVDIMM application. PMIC is used for switching and LDO regulators. PMIC-I3C Interface used to select suitable power fit for various application environment. PMIC device is intended to operate up to 12.5MHz.

Key Features

Maximum Operating speed 12.5MHz
Support In-band Interrupt
Bus reset is supported
Packet Error check(PEC)
Support Legacy I2C mode as well
I3C Basic Mode of Operation
Reset Dynamic Address Assignment Supported
7bit device Address
I2C Mode, Write, Read, Default Read Address Pointer mode
I3C Basic target mode, Supports

Write Operation
Read Operation
Packet Error Code (PEC) Supported
Default Read Address Pointer mode

Parity Error Handling Support
CCC Packet Error Handling Support
Enabled Parity Check and Error Reporting
I3C Basic Common Command Codes (CCC)

DEVCTRL
SETHID
SETAASA
ENEC
DISEC
RSTDAA
DEVCAP
GETSTATUS

Interrupt Arbitration Process support for multiple devices
jesd301-1 specification compliance
MIPI I3C Basic specification compliance

Block Diagram

Applications

DDR5 DIMM Application Environment
DDR5 NVDIMM Application Environment
Automotive Devices
Memory Devices
Power Mangement Devices
Defense / Aerospace / Customer Electronics

Deliverables

Verilog Source code
User Guide
IP Integration Guide
Simulation Script
Synthesis Script
Encrypted UVM Verification Environment
cocotb Verification Environment
Basic Testsuite
Firmware code

Technical Specifications

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