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PLL

Overview

The Innosilicon’s high performance PLL is a high speed, low jitter frequency synthesizer and developed as an IP block to reduce time to market, risk and cost in the development of AFE (Analog Front-End) design. It can generate stable high-speed clock from an ultra-wide input clock. With excellent supply noise immunity, the PLL is ideal for using in noisy mixed signal SoC environments. This PLL integrates a Phase Frequency Detector (PFD), a Low Pass Filter (LPF), a Voltage Controlled Oscillator (VCO) and other associated circuits. All fundamental building blocks as well as fully programmable dividers are integrated in the core.

Key Features

  • Dual power supply: 1.8V (analog) & 0.8V(digital) allow for excellent supply noise rejection
  • Input reference clock frequency supports ranging from 10MHz to 500MHz
  • PFD frequency supports ranging from 10MHz to 100MHz
  • VCO frequency supports ranging from 1GHz to 3.2GHz
  • Low jitter
  • Built-in lock detector to indicate the frequency lock state

Technical Specifications

Foundry, Node
TSMC 55/40/28/22/12/7/6/5/4/3nm, Samsung 28/14/10/8/5/4nm, SMIC 55/40/14nm, GF 55/28/22/12nm, UMC 55/40/28/22nm, HLMC 55/40/28nm
GLOBALFOUNDRIES
In Production: 12nm , 22nm FDX , 28nm LPH , 55nm LPX
Silicon Proven: 12nm , 22nm FDX , 28nm SLP , 55nm LPX
SMIC
In Production: 14nm , 40nm LL , 55nm LL
Silicon Proven: 14nm , 40nm LL , 55nm LL
Samsung
In Production: 4nm , 5nm , 8nm , 10nm , 14nm , 28nm FDS , 28nm LPP
Silicon Proven: 4nm , 5nm , 8nm , 10nm , 14nm , 28nm FDS , 28nm LPP
TSMC
In Production: 12nm , 22nm , 28nm HPC , 28nm HPCP , 28nm HPM , 40nm G , 40nm LP , 55nm LP
Silicon Proven: 3nm , 4nm , 5nm , 6nm , 7nm , 12nm , 22nm , 28nm HPC , 28nm HPCP , 28nm HPM , 40nm G , 40nm LP , 55nm LP
UMC
In Production: 22nm , 28nm HPC , 55nm
Silicon Proven: 22nm , 28nm HPC , 55nm
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