Innosilicon CSI-2 Receiver implements CSI-2, MIPI D-PHY, and LVDS protocols. The CSI-2 link protocol specification is a part of group of communication protocols defined by MIPI Alliance standards intended for mobile system chip to chip communications. The CSI-2 specification is specially targets for Camera to Image application processor communication.
Innosilicon CSI-2 Receiver operates as a receiver of a CSI-2 link, which consists of an Innosilicon D-PHY, LVDS, and an Innosilicon CSI-2 controller.
? The Innosilicon D-PHY is used for the data transmission from a CSI-2 compliant camera sensor. In D-PHY, the link includes a High-Speed signaling for fast-data traffic and a low-power signaling mode for control purposes. Error information is generated for application layer to do further operation.
? Innosilicon LVDS implements the LVDS TIA/EIA protocol. Normally, Innosilicon LVDS contains five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit.
? The Innosilicon MIPI CSI-2 Receiver Controller works as a protocol layer between application layer and physical layer. It implements all three layers defined by CSI-2 Specifications, and aims to reconstruct the data stream from the D-PHY.
MIPI D-PHY Combo LVDS CSI-2 RX IP
Overview
Key Features
- Compliant with MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2) V1.3
- Compliant with MIPI Alliance Standard for D-PHY Specifications V1.2
- Compliant with LVDS IEEE Std1596.3-1996
- HS, LP, ULPS, and LVDS modes supported
- The data transfer rate range from 400Mbps to 2.5Gbps per lane (D-PHY)
- 1.2Gbps maximum data transfer rate per lane under LVDS mode
- Implements all three CSI-2 MIPI Layers (Pixel/Byte Packing Layer, Low Level Protocol and Lane Management)
- Supports high speed and low power lane operation
- Supports data type: RGB/YUV/RAW (Based on actual application scenarios)
- Supports virtual channel
- Supports for D-PHY Ultra Low Power State
- Error detection and correction supported
- Supports image pixel interface
- Dynamic configuration and control via core ports
Deliverables
- Databook and physical implementation guides Netlist (Spice format for LVS)
- Library Exchange Format (LEF)
- Encrypted Verilog Models
- GDSII to Foundry IP Merge
- Module integration guidelines
- Silicon validation report (when available)
Technical Specifications
Foundry, Node
SMIC 28nm
SMIC
In Production:
28nm
Silicon Proven: 28nm
Silicon Proven: 28nm
Related IPs
- MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI D-PHY/LVDS Combo CSI-2 RX (Receiver) in TSMC 28HPC+
- MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- MIPI C-PHY-D-PHY Combo PHY IP on TSMC 28nm HPC+
- MIPI CSI-2 controller Receiver v 2.1, Compatible with MIPI C-PHY v1.2 & DPHY v2.1.
- Camera MIPI D-PHY v1-1 1.5Gbps / sub-LVDS combo Receiver 4-Lane