MIPI D-PHY 4-Lane CSI2-TX (Transmitter) in TowerJazz 65nm
Overview
The MXL-DPHY-0p2G-CSI-2-TX-T-180BCD is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard for D-PHY. The IP is configured as a MIPI master optimized for camera interface applications (CSI-2). The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed data traffic while low power functions are mostly used for control.
Key Features
- Consists of 1 Clock lane and up to 4 Data lanes
- Supports MIPI Standard 2.1 for D-PHY
- Supports both high speed and low-power modes
- 80 Mbps to 1.2Gbps data rate in high speed mode
- 10 Mbps data rate in low-power mode
- High Speed Serializer included
- Low power dissipation
Benefits
- Comprehensive embedded DFT features for allowing cost-effective high-volume manufacturing tests.
Block Diagram
Applications
- Mobile
- Cameras/Sensors
- IoT
- VR/AR/MR
- Consumer electronics
- Automotive
Deliverables
- Specifications
- GDSII
- LVS netlist
- LEF file
- IBIS Model
- Verilog Model
- Timing Model
- Integration Guidelines
- RTL
- Documentation
- One year support
Technical Specifications
Foundry, Node
TowerJazz, 65nm ISC
Maturity
Silicon Proven
Availability
Now