IP Catalog > Interface IP > Other > LVDS TX PHY & Controller

LVDS TX PHY & Controller

Overview

Innosilicon LVDS implements LVDS TIA/EIA protocol. It specifies a low-voltage point-to-point signal interface, which uses a differential driver connected to a terminated receiver through a constant-impedance transmission line. Normally, Innosilicon LVDS contains serial-to-parallel logic, PLL and register bank. It can be configured by registers through APB bus.
In addition, Innosilicon LVDS could extend from 5 lanes to N lanes (N is required by the customer). Therefore, the TTL lines extend respectively.

Key Features

  • Compatible with 900mV Vcom sub-LVDS standard
  • LVDS Display Serdes Interfaces directly to LCD Display Panels with Integrated LVDS
  • Suited for Display Resolutions Ranging from HVGA up to HD with Low EMI
  • Supports 4 data lanes and 1 clock lane mode, the data lane is extended according to customers.
  • Meet or exceed the requirements of 900mV Vcom sub-LVDS standard
  • Supports byte clock for LVDS mode
  • Supports the input signals clock edge and data edge align
  • Supports 7-bit parallel output per data lane in LVDS mode
  • Supports data rate up to 1.2Gbps per lane for LVDS mode
  • Typical input Impedance 100?
  • Dual channels supported
  • BIST with built-in PRBS
  • Embedded ESD, boundary scan support logic

Deliverables

  • Databook and physical implementation guides Netlist (Spice format for LVS)
  • Library Exchange Format (LEF)
  • Encrypted Verilog Models
  • GDSII to Foundry IP Merge
  • Module integration guidelines
  • Silicon validation report (when available)
  • Evaluation board (when available)

Technical Specifications

Foundry, Node
SMIC 40/28/12nm, TSMC 28/22/16/12nm, Samsung 28/14nm
SMIC
In Production: 40nm LL
Silicon Proven: 28nm HKC+
Samsung
In Production: 14nm
Pre-Silicon: 28nm FDS , 28nm LPP
TSMC
In Production: 12nm , 16nm
Pre-Silicon: 28nm HPC , 28nm HPCP , 28nm HPM
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