DisplayPort Receiver Link Controller
Overview
Our 5th generation DisplayPort Receiver Link Controller core supports DisplayPort 1.4, 2.0 and embedded DisplayPort 1.4b features, including link rates up to 8.1 Gbps. The highly integrated and configurable base core design includes all required link functionality—Main Link, Secondary Channel, and AUX Channel protocols. It also supports optional Display Stream Compression (DSC), Forward Error Correction (FEC), multi-stream transport (MST), and HDCP standards for data encryption. The DisplayPort Receiver core interfaces use common industry standards for low-complexity integration—with or without a host CPU.
Key Features
- Silicon proven on multiple ASIC and FPGA processes
- Capable of operating without a host CPU in low complexity applications
- Horizontal and vertical video delimiter signals with 1, 2 or 4 pixels per output cycle, supporting up to 16K resolution output; deep color and HDR support
- 1.62 to 8.1 Gbps link rate across 1, 2, or 4 lanes
- Secondary channel support, including audio and camera/video information packets
- MST support for 1 to 4 streams
- HDCP 1.3/2.2/2.3 support in SST and MST modes
- Optional eDP 1.4b supports PSR and PSR2
- DSC transport with Forward Error Correction support
- Interfaces to external PHY implementations in both FPGA and ASIC platforms
- Compatible with 3rd party PHYs
Block Diagram
Deliverables
- HDL source files for the function design
- HDL source files for basic core testing
- User’s Guide
- Integrator’s Guide
- Timing constraints summary document
- Generic SRAM simulation models
- C Reference Driver
Technical Specifications
Foundry, Node
65nm, 40nm, 28nm, 14nm
Maturity
In Production
Availability
Immediate