Forward Error Correction IP

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Compare 87 Forward Error Correction IP from 19 vendors (1 - 10)
  • HDMI 2.1 FEC Receiver (Tx)
    • HDMI 2.1 compliant
    • Reed-Solomon RS (255,251) FEC, 8-bit symbols
    • Supports 3-lane and 4-lane operation
    • Error counters included (Rx only)
    Block Diagram -- HDMI 2.1 FEC Receiver (Tx)
  • Viterbi Decoder
    • Hard or soft decoder with configurable soft bit widths
    • Parameterisable generator polynomials
    • Parameterisable code Constraint length
    Block Diagram -- Viterbi Decoder
  • Block Diagram -- Error Correction IP
  • Polar Encoder / Decoder for 3GPP 5G NR
    • Fully compliant with the 3GPP NR standard for PUCCH, PUSCH, PDCCH and PBCH. Supports the full range of uncoded and encoded block sizes
    • Implements the entire Polar encoding and decoding chain in 3GPP TS38.212
    • High error correction performance from Polar PC/CRC-aided decoder core
    • Tightly integrates the components in the chain to reduce area usage and latency
    Block Diagram -- Polar Encoder / Decoder for 3GPP 5G NR
  • DOCSIS 3.1 LDPC Decoder (PLC / NCP / Data)
    • Soft-Decision Demapper, Derandomizer, Deinterleaver, Depuncturer, and LDPC Decoder are included
    • Support for 4k and 8K FFT sizes
    • Support for 16-QAM modulation
    Block Diagram -- DOCSIS 3.1 LDPC Decoder (PLC / NCP / Data)
  • 66/2112 Codec for Cyclic Code (2112,2080)
    • Small Size
    • Implements FEC Sublayer for 10GBASE-R (section 74 of the IEEE 802.3 standard)
    • 10G/40G/100G Ethernet MAC-friendly interface
    • Practically self-contained: requires only memory for one 2112-bit block in the decoder.
    Block Diagram -- 66/2112 Codec for Cyclic Code (2112,2080)
  • SDA OCT V3.0 Encoder and Decoder
    • Compliant with "Optical Communications Terminal (OCT) Standard Version 3.0, Document ID: SDA-9100-0001-05, August 2021"
    • Support for payload code rates 11/13, 22/29, 2/3, 1/2, and uncoded data
    Block Diagram -- SDA OCT V3.0 Encoder and Decoder
  • DVB-GSE Encapsulator and Decapsulator
    • Compliant with ETSI TS 102 606-1 V1.2.1 (Annex D, DVB-GSE Lite)
    • Support for multi-protocol encapsulation (IPv4, IPv6, MPEG, Ethernet, etc.)
    Block Diagram -- DVB-GSE Encapsulator and Decapsulator
  • BCH Encoder/Decoder
    • BCH decoder compliant with the DVB-T2/S2 standard.
    • Available for Altera/Xilinx FPGA or ASIC implementation.
    • High speed design.
    • BCH decoder works on GF(2M) where M = 16 or 14 and correctup to T errors where T = 10 or 12.
    Block Diagram -- BCH Encoder/Decoder
  • DVB-S2X Multi-Carrier Demodulator
    • Supports CCM, ACM and VCM
    • Supports roll-off factors 5%, 10%, 15%, 20%, 25% to 35%
    • Support for short and normal blocks (16,200 bits and 64,800 bits) with pilots only
    • Support for QPSK to 256-APSK
    Block Diagram -- DVB-S2X Multi-Carrier Demodulator
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