Who should worry about Xilinx and Oasys partnership?
June 14, 2010
Xilinx announced that it signed a multi-year strategic licensing agreement to use Oasys’ synthesis. What does that mean for the FPGA and EDA community?
Oasys’ product, RealTime Designer, is claimed to be 10x-60x faster than the competition. Among other things, it uses AIG-based optimization. This technology is best illustrated by UC Berkeley’s ABC synthesis: several FPGA startups reported that ABC boosted significantly the speed, capacity, and quality of their synthesis engines. No question that Oasys’ synthesis is competitive, at least in the FPGA world.
To read the full article, click here
Related Semiconductor IP
- Root of Trust (RoT)
- Fixed Point Doppler Channel IP core
- Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
- Polyphase Video Scaler
- Compact, low-power, 8bit ADC on GF 22nm FDX
Related Blogs
- Oasys or Mirage?
- PLD Overview: Xilinx and Altera
- What to read in Xilinx' and Altera's third quarter results
- Xilinx ARMs itself for battle
Latest Blogs
- Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)
- The Industry’s First USB4 Device IP Certification Will Speed Innovation and Edge AI Enablement
- Understanding Extended Metadata in CXL 3.1: What It Means for Your Systems
- 2025 Outlook with Mahesh Tirupattur of Analog Bits
- eUSB2 Version 2 with 4.8Gbps and the Use Cases: A Comprehensive Overview