Who should worry about Xilinx and Oasys partnership?
June 14, 2010
Xilinx announced that it signed a multi-year strategic licensing agreement to use Oasys’ synthesis. What does that mean for the FPGA and EDA community?
Oasys’ product, RealTime Designer, is claimed to be 10x-60x faster than the competition. Among other things, it uses AIG-based optimization. This technology is best illustrated by UC Berkeley’s ABC synthesis: several FPGA startups reported that ABC boosted significantly the speed, capacity, and quality of their synthesis engines. No question that Oasys’ synthesis is competitive, at least in the FPGA world.
To read the full article, click here
Related Semiconductor IP
- SoC Security Platform / Hardware Root of Trust
- SPI to AHB-Lite Bridge
- Octal SPI Master/Slave Controller
- I2C and SPI Master/Slave Controller
- AHB/AXI4-Lite to AXI4-Stream Bridge
Related Blogs
- Oasys or Mirage?
- PLD Overview: Xilinx and Altera
- What to read in Xilinx' and Altera's third quarter results
- Xilinx ARMs itself for battle