How can Xilinx improve its bottom line
Last week I wrote a post discussing Xilinx and Altera Q3’09 results, and I mentioned Xilinx’ operation margin consistently trailing Altera’s by 3-4%. I had a few emails regarding that gap, and why that gap would be closed eventually. Let me address this topic with this post.
Comparing the yearly fiscal exercises directly would be biased (Xilinx’ fiscal year end on March 31st, and Altera’s fiscal year on Dec 31st). Instead we can look at a quarter by quarter comparison, even though that can be too low a level. Better is to look for ttm (trailing twelve months) comparison to smooth out the local variations.
To read the full article, click here
Related Semiconductor IP
- SoC Security Platform / Hardware Root of Trust
- SPI to AHB-Lite Bridge
- Octal SPI Master/Slave Controller
- I2C and SPI Master/Slave Controller
- AHB/AXI4-Lite to AXI4-Stream Bridge
Related Blogs
- PLD Overview: Xilinx and Altera
- What to read in Xilinx' and Altera's third quarter results
- Xilinx ARMs itself for battle
- Xilinx ARMs FPGAs, Altera to MIPSify Them