Can Tabula and Tier Logic be successful?
The past two weeks were pretty interesting if you follow FPGAs. Yes, Xilinx and Altera kept upping their target to Wall St., but that is not where the excitement came from. It came from the recent announcements of two startups, both created in 2003 and heavily funded. Tabula released its long-awaited device, which goes by the sexy name of “Spacetime”. And Tier Logic left its stealth mode this week to announce its own device, “TierFPGA”.
The dominant factor in classical FPGA architecture is the interconnect: most of the die area is taken by the wires and the interconnect switches and muxes. If you can somehow reduce the area dedicated to interconnect, you can augment the logic density and lessen the cost of the device. Tabula and Tier Logic pitch a 3D architecture to address the interconnect bottleneck, albeit in very different flavors.
To read the full article, click here
Related Semiconductor IP
- UCIe Chiplet PHY & Controller
- MIPI D-PHY1.2 CSI/DSI TX and RX
- Low-Power ISP
- eMMC/SD/SDIO Combo IP
- DP/eDP
Related Blogs
- RIP Tier Logic
- Open-Silicon adds Silicon Logic Engineering - for a good reason
- Fixed logic to give 28nm FPGAs a helping hand
- What Can We Learn From The iPad About Chip Design?
Latest Blogs
- Cycuity Partners with SiFive and BAE Systems to Strengthen Microelectronics Design Supply Chain Security
- Cadence Unveils the Industry’s First eUSB2V2 IP Solutions
- Half of the Compute Shipped to Top Hyperscalers in 2025 will be Arm-based
- Industry's First Verification IP for Display Port Automotive Extensions (DP AE)
- IMG DXT GPU: A Game-Changer for Gaming Smartphones