Creating SystemC TLM-2.0 Peripheral Models
July 18, 2011
Over two years ago, I made some experiments and raised some requirements for an effective Virtual Platform IP authoring tool. Even with the passage of time, some people seem to find it useful as I regularly get questions about it. It is more than time to give you an update, and the good news is that such a tool is now available as part of the new Cadence Virtual System Platform (VSP) product. One of the capabilities provided by the Virtual System Platform is a tool to enable easy authoring of Virtual Platform IP models.
To read the full article, click here
Related Semiconductor IP
- UCIe Chiplet PHY & Controller
- MIPI D-PHY1.2 CSI/DSI TX and RX
- Low-Power ISP
- eMMC/SD/SDIO Combo IP
- DP/eDP
Related Blogs
- SystemC TLM-2.0 Virtual Platform Direct Memory Interface (DMI) Performance Impact
- Semiconductor cost models
- Cowan LRA model's 2010 semicon sales growth forecast estimate: How does it "stack up" against other prognosticators?
- De-Mystifying SystemC: What is TLM?
Latest Blogs
- Cadence Unveils the Industry’s First eUSB2V2 IP Solutions
- Half of the Compute Shipped to Top Hyperscalers in 2025 will be Arm-based
- Industry's First Verification IP for Display Port Automotive Extensions (DP AE)
- IMG DXT GPU: A Game-Changer for Gaming Smartphones
- Rivos and Canonical partner to deliver scalable RISC-V solutions in Data Centers and enable an enterprise-grade Ubuntu experience across Rivos platforms