Creating SystemC TLM-2.0 Peripheral Models
July 18, 2011
Over two years ago, I made some experiments and raised some requirements for an effective Virtual Platform IP authoring tool. Even with the passage of time, some people seem to find it useful as I regularly get questions about it. It is more than time to give you an update, and the good news is that such a tool is now available as part of the new Cadence Virtual System Platform (VSP) product. One of the capabilities provided by the Virtual System Platform is a tool to enable easy authoring of Virtual Platform IP models.
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Related Semiconductor IP
- I2C Controller IP – Slave, Parameterized FIFO, Avalon Bus
- I2C Controller IP – Master, Parameterized FIFO, Avalon Bus
- I2C/SMBus Controller IP – Master / Slave, Parameterized FIFO, AXI/AHB/APB/Avalon Buses, SMBus Protocol
- I2C Controller IP- Master / Slave, Parameterized FIFO, Avalon Bus
- I3C Controller IP – I3C / I2C Slave, Configure User Registers, no CPU Host Required
Related Blogs
- SystemC TLM-2.0 Virtual Platform Direct Memory Interface (DMI) Performance Impact
- Semiconductor cost models
- Cowan LRA model's 2010 semicon sales growth forecast estimate: How does it "stack up" against other prognosticators?
- De-Mystifying SystemC: What is TLM?