RISC-V: When a bug really is a feature
April 26, 2017
How the RISC-V memory model bug shows the real power of an open ISA.
No doubt some of you have read about the problem in the proposed RISC-V memory model that received a lot of publicity last week (http://www.princeton.edu/engineering/news/archive/?id=17707), and if you have, it’s also worth looking at the formal response on the RISC-V website (https://riscv.org/2017/04/risc-v-memory-consistency-model/). They talk a lot about the technical details, which is not what I plan on discussing today.
So what does this mean for the growing number of people adopting RISC-V?
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