RISC-V: When a bug really is a feature
How the RISC-V memory model bug shows the real power of an open ISA.
No doubt some of you have read about the problem in the proposed RISC-V memory model that received a lot of publicity last week (http://www.princeton.edu/engineering/news/archive/?id=17707), and if you have, it’s also worth looking at the formal response on the RISC-V website (https://riscv.org/2017/04/risc-v-memory-consistency-model/). They talk a lot about the technical details, which is not what I plan on discussing today.
So what does this mean for the growing number of people adopting RISC-V?
To read the full article, click here
Related Semiconductor IP
- MIPI I3C Master RISC-V based subsystem
- ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core
- RISC-V CPU IP
- RISC-V Vector Extension
- RISC-V Real-time Processor
Related Blogs
- Analog Bits and SEMIFIVE is a Really Big Deal
- AI: when is it "really" intelligent?
- Processor architecture optimization is not a barrier for university researchers
- SiFive Makes a Splash at the RISC-V Summit with 10+ Talks, Demos, and a Surprise Product Reveal
Latest Blogs
- Cadence Unveils the Industry’s First eUSB2V2 IP Solutions
- Half of the Compute Shipped to Top Hyperscalers in 2025 will be Arm-based
- Industry's First Verification IP for Display Port Automotive Extensions (DP AE)
- IMG DXT GPU: A Game-Changer for Gaming Smartphones
- Rivos and Canonical partner to deliver scalable RISC-V solutions in Data Centers and enable an enterprise-grade Ubuntu experience across Rivos platforms