How far can multicore SoC scaling go? Cavium's Octeon II
In network switching applications, multicore SoC architectures appear to be crossing a threshold between two paradigms. When multicore chips first appeared there was a clear distinction in the hardware between the control and data planes. One or a few general-purpose CPU cores sat in the control plane with their own caches and their own—usually AMBA—bus structure. A cluster of special-purpose processors sat in the data plane with their own buffers and interconnect scheme, and a bridge to the control-plane bus.
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