BDTI unveils FPGA C-synthesis certification: Can C beat RTL?
With the appearance of higher speeds and more DSP macrocells in low-cost FPGAs, more and more design teams are seeing the configurable chips not as glue, but as a way to accelerate the inner loops of numerical algorithms, either in conjunction with or in place of the traditional DSP chip. It's well understood that encoding critical kernels in an FPGA can increase performance by more than an order of magnitude compare to even the fastest DSP chip, often reducing energy consumption as well.
To read the full article, click here
Related Semiconductor IP
- 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
- ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
- High-Speed 3.3V I/O library with 8kV ESD Protection in TSPCo 65nm
- Verification IP for DisplayPort/eDP
- Wirebond Digital and Analog Library in TSMC 65nm
Related Blogs
- Open ARM-wrestling in FPGAs
- Why FPGA startups keep failing
- Over-interpreting the extended ARM
- Lattice sticks with open RISC
Latest Blogs
- Half of the Compute Shipped to Top Hyperscalers in 2025 will be Arm-based
- Industry's First Verification IP for Display Port Automotive Extensions (DP AE)
- IMG DXT GPU: A Game-Changer for Gaming Smartphones
- Rivos and Canonical partner to deliver scalable RISC-V solutions in Data Centers and enable an enterprise-grade Ubuntu experience across Rivos platforms
- ReRAM-Powered Edge AI: A Game-Changer for Energy Efficiency, Cost, and Security