Lattice sticks with open RISC
November 11, 2009
Most of the attention in the release on Lattice Semiconductor’s Version 8.0 of ispLEVER was on the software’s expansion of DDR support – all well and good, mind you, given the expansion of DDR2 in the embedded space. But I was more interested in the expansion of the RISC Lattice Mico32 development system. The environment now includes a newer version of a GNU compiler, and a triple-speed MAC IP core. Lattice also announced it would be working with Beyond Semiconductor on compiler tools for Mico32.
There are wags out there who will say that “Those who can, brand their RISC, those who can’t, go open source.
To read the full article, click here
Related Semiconductor IP
- Root of Trust (RoT)
- Fixed Point Doppler Channel IP core
- Multi-protocol wireless plaform integrating Bluetooth Dual Mode, IEEE 802.15.4 (for Thread, Zigbee and Matter)
- Polyphase Video Scaler
- Compact, low-power, 8bit ADC on GF 22nm FDX
Related Blogs
- Have you checked the hidden costs of deploying an open source RISC-V core?
- Open Source vs Commercial RISC-V Licensing Models
- Closing the Gap in SoC Open Standards with RISC-V
- Experts Talk: RISC-V CEO Calista Redmond and Maven Silicon CEO Sivakumar P R on RISC-V Open Era of Computing
Latest Blogs
- Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)
- The Industry’s First USB4 Device IP Certification Will Speed Innovation and Edge AI Enablement
- Understanding Extended Metadata in CXL 3.1: What It Means for Your Systems
- 2025 Outlook with Mahesh Tirupattur of Analog Bits
- eUSB2 Version 2 with 4.8Gbps and the Use Cases: A Comprehensive Overview