What you need to know about EDA360
June 1, 2010
Cadence unveiled EDA360 in April. Now that I found the time to read its 28-pages white paper, I can finally comment on it.
EDA360, John Bruggeman’s brainchild, is a manifesto that promotes a vision for the future of EDA. In a nutshell, it states the following:
- So far EDA has been providing the tools to IC creators: design, implement, and verify ICs.
- With the development cost of 32nm SoC reaching $100M, only a handful of semiconductor companies will still create ICs in the next future.
- With modern consumer electronics fueled by apps-based model, electronic design is moving from a hardware-first to a software-centric industry.
- Future SoC will be designed top-down, with software and apps requirements driving the integrations of IPs, DSPs, GPUs, CPUs and cores (ARM, MIPS, x86, etc).
- EDA needs to provide the environment for integrating and optimizing software and hardware resources.
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related Blogs
- Cadence EDA360 Redux!
- EDA360 Is More Than Design IP Plus Software Drivers
- ARM's Cortex-A15: A big step up for the ARM processor architecture. Targeting 32nm and 28nm technology nodes
- When will you be facing these 28nm design challenges?
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?