Busses, Crossbars and NoCs: The 3 Eras of SoC Interconnect History

By _Arteris Connected Blog

October 25, 2010

Today the processor in your Blackberry or iPhone has more calculating power than a PC did only a decade ago. No surprise here. But how did this happen? What enabled this?

The pat answer of course is “Moore’s law enabled semiconductor designers to cram more transistors into a given area each year, allowing more functions to be added to a chip.”

True.

But what is more interesting is the history of the critical part of the system that ties together all these functional IP blocks. I’m talking about the history of the interconnect.

The history of the interconnect has three phases. The first phase was driven by busses, with the first de-facto commercial standard being ARM’s Advanced Microcontroller Bus Architecture (AMBA). Originally released in 1996, AMBA consisted of two busses:  An Advanced System Bus (ASB) for general SoC IP interconnect and an Advanced Peripheral Bus (APB) for slower peripherals. ARM followed these with the introduction of the Advanced High-performance Bus (AHB) to replace the ASB. However, many companies continued to own and developer their own bus interconnect IP.

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