Arteris expands their approach to Networks on Chips
As SoCs become more complex, the concept of using a network to replace the bus or crossbar switch as the interconnect backbone on the chip has become more popular. From thesis material a few years ago, the NoC is now actually shipping, carefully buried in some consumer products.
Related Semiconductor IP
- RISC-V CPU IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
Related Blogs
- NoC Interconnect Technology Becoming Mainstream
- Arteris vs Sonics battle...Let's talk NoC architecture
- The Gartner Hype Cycle & Technology Adoption Lifecycle Explained (using NoC Technology)
- Hogan NoC analysis - Sonics SGN, Arteris FlexNoC, ARM NIC 400: Setting the record straight
Latest Blogs
- Why Choose Hard IP for Embedded FPGA in Aerospace and Defense Applications
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
- Quintauris: Accelerating RISC-V Innovation for next-gen Hardware
- Say Goodbye to Limits and Hello to Freedom of Scalability in the MIPS P8700
- Why is Hard IP a Better Solution for Embedded FPGA (eFPGA) Technology?