How to design a 40-billion-transistor SoC (and live to tell the tale)
Keynoting the Mentor Graphics U2U meeting in Santa Clara this morning, Mentor chairman and CEO Wally Rhines delivered one of his signature tightly-reasoned essays on the future of IC design and what we might do about it. The topic was, roughly, SoC design in 2018.
Rhines started with his frequent observation that Moore's Law is actually not a law, but more of an observation. And at that, it is a particular case of a learning curve: that nearly universal law of human endeavor that mandates a linear relationship between the log of unit cost and the log of cumulative volume. Extrapolating from the days of vacuum tubes through the ups and downs of recent years and into the dark sub-nanometer future, Rhines pegged the headline chips of 2018 at 40 billion transistors each.
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