IP Catalog > Interface IP > Interconnect IP > USB IP > USB 3.0 IP

USB 3.0 IP

Welcome to the ultimate USB 3.0 IP hub! Explore our vast directory of USB 3.0 IP
All offers in USB 3.0 IP
Filter
Filter

Login required.

Sign in

Login required.

Sign in

Search (174)
Compare 174 USB 3.0 IP from 23 vendors (1 - 10)
  • MIPI M-PHY - TSMC 40nm
    • Compliant to MIPI Alliance Standard for M-PHY specification Version 3.0
    • •Supports high speed data transfer G1A/B, G2A/B and G3A/B with data rates of up to 5830.4 Mbps
    • •Supports M-PHY Type-I system
    • •Support for reference clock frequencies of 19.2MHz/26MHz/38.4MHz/52MHz
    Block Diagram -- MIPI M-PHY - TSMC 40nm
  • Block Diagram -- A 65nm Wirebond IO library with 1-3.3V GPIO, 3.3V pulse-width modulation cell, I2C & SVID open-drain, 3.3V & 5V analog and OTP program cell
  • MIPI M-PHY Designed For GF 28nm
    • •Compliant to MIPI Alliance Standard for M-PHY specification Version 3.0
    • •Supports high speed data transfer G1A/B, G2A/B and G3A/B with data rates of up to 5830.4 Mbps
    • •Supports M-PHY Type-I system
    • •Support for reference clock frequencies of 19.2MHz/26MHz/38.4MHz/52MHz
    Block Diagram -- MIPI M-PHY Designed For GF 28nm
  • USB3.0 PHY
    • Silicon proven in 22, 28, Global Foundries and Samsung
    • Spread Spectrum clock (SSC) and data scrambling to minimize EMI
    • Supports 16-bit 250-MHz , and 32-bit 125M PIPE interface
    • Multiple loopback and compliance test modes
    Block Diagram -- USB3.0 PHY
  • USB3.0 PHY on GF22FDX and Samsung 28nm FDSOI
    • The USB3.0 PHY IP is designed according to the USB 3.0, USB2.0 Specification.
    • It supports the USB3.0 5Gbps Super-Speed mode and backward compatibles with the USB2.0 480Mbps High-Speed, 12Mbps Full-Speed, and 1.5Mbps Low-Speed modes
    • The USB 3.0 PHY interface complies with PHY Interface for PCI Express and USB3.0 Architectures specification (PIPE 3.0) and the USB2.0 PHY interface complies with the UTMI v1.05 specification.
       
    Block Diagram -- USB3.0 PHY on GF22FDX and Samsung 28nm FDSOI
  • USB 3.0 SSIC PHY
    • Compliant with SSIC specification 1.0
    • Compliant with MIPI-MPHY (Type-1) specification Rev 3.0-r.03
    Block Diagram -- USB 3.0 SSIC PHY
  • USB HSIC PHY - High Speed Inter-Chip IP Core
    • High-Speed 480Mbps data rate only
    • Source-synchronous seriel interface
    • No power consumed unless a transfer is in progress.
    • Maximum trace length of 10cm
    Block Diagram -- USB HSIC PHY - High Speed Inter-Chip IP Core
  • USB 3.0 Device Controller
    • USB 3.0 Compliance
    • 8/16/32 bit USB 3.0 PIPE interface
    • 8/16 UTMI/ULPI interface
    • Master DMA implementation for each endpoint with Scatter Gather support
    Block Diagram -- USB 3.0 Device Controller
  • SuperSpeed USB 3.0 Host Controller Supporting SSIC and HSIC
    • Supports SuperSpeed USB power savings modes, Uniform Power Format (UPF) and dual power rails
    • Lowers overall system power by design
    • Configurable data buffering options to fine-tune performance/area trade-offs
    • Host supports SuperSpeed, High-Speed, Full-Speed, and Low-Speed operation
    Block Diagram -- SuperSpeed USB 3.0 Host Controller Supporting SSIC and HSIC
  • SuperSpeed USB 3.0 Dual Role Device Controller, Configurable for SSIC and HSIC
    • Supports SuperSpeed USB power savings modes, Uniform Power Format (UPF) and dual power rails
    • Lowers overall system power by design
    • Configurable data buffering options to fine-tune performance/area trade-offs
    • Host supports SuperSpeed, High-Speed, Full-Speed, and Low-Speed operation
    Block Diagram -- SuperSpeed USB 3.0 Dual Role Device Controller, Configurable for SSIC and HSIC
×
Semiconductor IP