USB IP

USB PD 3.1 compliant.
Single chip solution – just two external capacitors.
4 pin package.
Less than 1mm2 area in 180nm.
PROM programmed through vendor message protocol.
Based on Obsidian’s mature PD technology.
Integrated PROM enables customized response to a wide range of vendor requirements.
Active Ra pulls down only requires 10uA at 5V., but is <1K below 2V.
Power <5mW. Enabled by CC data activity. I.e. very low duty cycle.
Programming can be done after assembly into the cable. Fuse lock function.
Supports low cost, 4 layer PCB assembly.

Complies with USB specifications Rev. 2.0 and 1.1
Complies with UTMI+ specification Level 3, Rev. 1.0
Supports 480Mb/s (HS), 12Mb/s (FS) and 1.5MB/s (LS) serial data transmission rates
Supports 8-bit unidirectional Parallel Interface Engine (PIE) bus for HS, FS and LS modes, and Serial Interface Engine (SIE) for FS and LS modes

Complies with USB specifications Rev. 2.0 and 1.1
Complies with UTMI+ specification Level 3, Rev. 1.0
Supports 480Mb/s (HS), 12Mb/s (FS) and 1.5MB/s (LS) serial data transmission rates
Supports 8-bit unidirectional Parallel Interface Engine (PIE) bus for HS, FS and LS modes, and Serial Interface Engine (SIE) for FS and LS modes

Mixed signal Analog Front End Macros for 65n, 130n, 150nm, and 180n technologies.
RTL code from AFE to I2C compatible register set.
Stand alone C code for Protocol, Device Policy Manager, and System Policy Manager.
IP demonstration & development board, with compliance reports.
Full chip integration of USB Type-C, and associated software.

Fully transparent design eliminates the need for Host configuration and management software
Built-in support for PIPE-attached embedded endpoints (including 64-bit PIPE) for reduced BoM, latency, and power
Seamless implementation on ASIC and FPGA with same RTL code base, up to x8 Gen4 per port on FPGA (or x16 Gen3)
Lowest latency switching logic on the market (2 clock cycles)

Compliant with USB2.0 and USB1.1 specification
Compliant with UTMI Specification Version level 3.
Supports HS(480Mbps)/FS(12Mbps) /LS(1.5Mbps) modes
All required terminations, including 1.5Kohm pullup on DP and DM, and 15Kohm pull-down on DP and DM are internal to chip

Compliant to MIPI Alliance Standard for M-PHY specification Version 3.0
•Supports high speed data transfer G1A/B, G2A/B and G3A/B with data rates of up to 5830.4 Mbps
•Supports M-PHY Type-I system
•Support for reference clock frequencies of 19.2MHz/26MHz/38.4MHz/52MHz

Complies with USB specifications, rev. 2.0 and 1.1
Complies with UTMI+ specification, level 3, rev. 1.0
Supports 480Mb/s (HS), 12Mb/s (FS) and 1.5MB/s (LS) serial data transmission rates
Supports 8-bit unidirectional Parallel Interface Engine (PIE) bus for HS, FS and LS modes, and Serial Interface Engine (SIE) for FS and LS modes

Complies with Universal Serial Bus Specification Rev. 2.0
Interface compliant with the UTMI specification (60MHz 8-bit interface or 30MHz 16-bit interface)
Supports 480Mbps High-Speed(HS) and 12Mbps Full-Speed(FS)