Subsystem IP: The Implications Reach Beyond the Chip
Ron Wilson, Altera
May 18, 2015
The appearance of subsystem-scale intellectual property (subsystem IP) cores a few years ago triggered a glacial shift in system-on-a-chip (SoC) design: slow, inexorable, but shoving before it a mound of unintended consequences. As cell-based SoCs and even FPGAs incorporating subsystem IP appear in real systems, we are seeing that those consequences extend even beyond the boundaries of the chip.
The concept of subsystem IP is unassailably appealing—it is simply an extension of design reuse further up the hierarchy. If reusing an interface block is good, why not reuse an entire audio subsystem, or machine vision subsystem, or whatever? In effect, we are picking up an entire modest-sized SoC, including its CPUs, accelerators, memory hierarchy, I/O controllers, and external interfaces, and instantiating it inside a larger chip.
To read the full article, click here
Related Semiconductor IP
- SLVS Transceiver in TSMC 28nm
- 0.9V/2.5V I/O Library in TSMC 55nm
- 1.8V/3.3V Multi-Voltage GPIO in TSMC 28nm
- 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
- ESD Solutions for Multi-Gigabit SerDes in TSMC 28nm
Related White Papers
- The pivotal role power management IP plays in chip design
- The Growing Market for Specialized Artificial Intelligence IP in SoCs
- Colibri, the codec for perfect quality and fast distribution of professional AV over IP
- The Complicated Chip Design Verification Landscape