Extreme Design: Realizing a single-chip CMOS 56 Gs/s ADC for 100 Gbps Ethernet
Ian Dedic, Fujitsu Microelectronics
8/25/2010 7:38 AM EDT
To provide a long-haul, 100-Gbps, optical transport network with maximum reach and immunity to optical fiber non-idealities, the industry has settled on dual-polarization quadrature phase-shift keying (DP-QPSK) as a modulation method, which means that a coherent receiver is required. The biggest implementation challenge resulting from this decision is the need for low-power ultra-high-speed ADCs, and their technology requirements define the way that such a receiver can be implemented.
A 100-Gbps coherent receiver needs four 56-Gs/s analog/digital converters (ADCs) and a tera-OPS DSP which dissipate only tens of watts. This paper discusses the forces pushing towards a single-chip CMOS solution, and the challenges in realizing this.
Related Semiconductor IP
- AES GCM IP Core
- High Speed Ethernet Quad 10G to 100G PCS
- High Speed Ethernet Gen-2 Quad 100G PCS IP
- High Speed Ethernet 4/2/1-Lane 100G PCS
- High Speed Ethernet 2/4/8-Lane 200G/400G PCS
Related White Papers
- Can 10 Gbps Ethernet be an Embedded Design Solution?
- Can 10 Gbps Ethernet be an Embedded Design Solution?
- 10-Gbit Ethernet revenues to reach $3.6 billion by '04, says Dataquest
- Testable SoCs : How systems level considerations impact cost-effective Gigabit Ethernet PHYs
Latest White Papers
- New Realities Demand a New Approach to System Verification and Validation
- How silicon and circuit optimizations help FPGAs offer lower size, power and cost in video bridging applications
- Sustainable Hardware Specialization
- PCIe IP With Enhanced Security For The Automotive Market
- Top 5 Reasons why CPU is the Best Processor for AI Inference