Developing DSP code on converged hybrid DSP/RISC cores

Recently processor designers have been reducing power consumption and part cost in a new way - by combining RISC and DSP features into a single core, known as a ‘convergent’ processor core.

Two examples of architectures that were designed from the beginning to be convergent are the Analog Devices Blackfin processor and StarCore processors (SC1000, SC2000, and SC v5). Some other examples of convergent architectures are based on well established RISC architectures and have been modified to efficiently fulfill DSP functions. These include the MIPS 24KE, Renesas SH3-DSP, PowerPC with AltiVec, and ARM966E-S.

Compared to standalone RISC systems, such convergent processors can be much more efficient at performing DSP tasks. Yet compared to traditional DSP processor designs, convergent processors generally have more complex pipelines and can run at high enough speeds to allow for fast control-intensive computing.

But even with the design simplification and improvements in production costs and power usage such hybrid architectures can offer to the developer, programming can still be a chore. The choice of tools can make a huge difference in the ability to bring a product to market quickly that is maintainable, robust, and uniquely poised for the challenges a successful product can bring.

For example, many of the DSP algorithms that can run on a converged processor have been written in assembly. Assembly programming provides the ultimate level of control over hardware and allows a clever programmer to squeeze every last drip of processing power out of a processor. As DSP applications get larger and more complex, the cost of programming in assembly consequently increases.

While it still may be useful to profile the DSP core and find the 20% of your code that takes 80% of the processing time and rewrite that code in assembly, the remainder of your code can be written in a higher level programming language.

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