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MACsec Engine IP

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Compare 26 MACsec Engine IP from 10 vendors (1 - 10)
  • MACsec - Extreme-Speed Variant
    • Moderate resource requirements
    • Performance
    • Standard Compliance
    Block Diagram -- MACsec - Extreme-Speed Variant
  • Media Access Control Security (MACSec)
    • Up to four ports of concurrent traffic with an aggregate bandwidth of 100G are supported by one core (1x100G, 2x50G, 2x40G, 4x25G, 4x10G, 4x1G, 1x50G+2x25G)
    • Line rate operation
    • Flexible control/non-control port filtering
    • Configurable number of Secure Channels (SCs) and Security Associations (SAs) per physical port
    Block Diagram -- Media Access Control Security (MACSec)
  • Secure-IC's Securyzr™ 1.5Tbps MACsec Engine
    • Throughput up to 1.5Tb
    • ASIC and FPGA
    • Multi-channel support for link aggregation or FlexE
    Block Diagram -- Secure-IC's Securyzr™ 1.5Tbps MACsec Engine
  • Ethernet IPSec/MACSec Switch/Router IP Core - Efficient and Massively Customizable
    • Full wire-speed on all ports and all Ethernet frame sizes.
    • Store and forward shared memory architecture.
    • Support for jumbo packets up to 32733 bytes.
    Block Diagram -- Ethernet IPSec/MACSec Switch/Router IP Core - Efficient and Massively Customizable
  • MACsec Protocol Engine for 10/100/1000 Ethernet
    • Compliant to IEEE 802.1AE-2018 and IEEE 802.1AEbw.
    • Implements both GCM-AES and GCM-AES-XPN modes with 128- and 256-bit keys.
    Block Diagram -- MACsec Protocol Engine for 10/100/1000 Ethernet
  • MACsec 10G/25G
    • Compliance with IEEE Std 802.1AE-2018
    • Line-rate traffic encryption and decryption
    • Supports 10G/25G data rates
    • Multiple Connectivity Associations (SecYs) with Traffic Mapping Rules
    Block Diagram -- MACsec 10G/25G
  • IEEE 802.1ae (MACsec) Security Processor
    • Small size combined with high performance:
    • Self-contained, uses two external memories for key storage and statistic counters
    • Very low latency
    • Back-to-back packet processing
    Block Diagram -- IEEE 802.1ae (MACsec) Security Processor
  • P1619/802.1ae (MACSec) GCM/XEX/XTS-AES Core
    • Small size: From 60K ASIC gates (at throughput of 18.2 bits per clock)
    • 487 MHz frequency in 90 nm process
    • Easily parallelizable to achieve higher throughputs
    • Completely self-contained: does not require external memory. Includes encryption, decryption, key expansion and data interface
    Block Diagram -- P1619/802.1ae (MACSec) GCM/XEX/XTS-AES Core
  • 10G-100G MACsec Security Module
    • Standards compliant (IEEE 802.1AE)
    • Solution standalone or integrated with Ethernet interface controllers
    • Per frame security processing including encapsulation/decapsulation and frame validation
    • Scalable throughput to 100+ Gbps based on pipelined AES-GCM cryptography with optimized latency
    Block Diagram -- 10G-100G MACsec Security Module
  • 1G-25G MACsec Security Module
    • Standards compliant (IEEE 802.1AE)
    • Solution standalone or integrated with Ethernet interface controllers
    • Per frame security processing including encapsulation/decapsulation and frame validation
    • Scalable throughput to 100+ Gbps based on pipelined AES-GCM cryptography with optimized latency
    Block Diagram -- 1G-25G MACsec Security Module
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