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HSIC IP

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Compare 4 IP from 4 vendors (1 - 4)
  • USB HSIC PHY - High Speed Inter-Chip IP Core
    • High-Speed 480Mbps data rate only
    • Source-synchronous seriel interface
    • No power consumed unless a transfer is in progress.
    • Maximum trace length of 10cm
    Block Diagram -- USB HSIC PHY - High Speed Inter-Chip IP Core
  • HSIC PHY
    • Consumes <90mW during data transfer
    • Consumes <50uW when not transferring data
    • Uses standard chip digital and IO supplies
    • Low pin count
  • USB 2.0 Host Controller
    • Supports Low Speed (1.5 Mbps), Full Speed (12 Mbps) and High Speed (480 Mbps)
    • Supports UTMI+Low Pin Interface (ULPI)
    • Supports ULPI PHY low power mode and register access through software
    • Supports 15 Bulk and 2 Interrupt Endpoints
  • AXI USB 2.0 Device Controller
    • AXI-4 based host Interface. AXI-4 Lite for Slave Interface and optional AXI-4 Master interface for DMA mode
    • Supports High Speed and Full Speed USB 2.0 specification
    • Supports high speed, high bandwidth isochronous transactions
    • Supports up to eight endpoints, including one control endpoint 0. Endpoints 1 to 7 can be bulk, interrupt, or isochronous and are individually configurable
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Semiconductor IP