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HSIC IP

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Compare 89 IP from 7 vendors (1 - 10)
  • SuperSpeed USB 3.0 Host Controller Supporting SSIC and HSIC
    • Supports SuperSpeed USB power savings modes, Uniform Power Format (UPF) and dual power rails
    • Lowers overall system power by design
    • Configurable data buffering options to fine-tune performance/area trade-offs
    • Host supports SuperSpeed, High-Speed, Full-Speed, and Low-Speed operation
    Block Diagram -- SuperSpeed USB 3.0 Host Controller Supporting SSIC and HSIC
  • SuperSpeed USB 3.0 Dual Role Device Controller, Configurable for SSIC and HSIC
    • Supports SuperSpeed USB power savings modes, Uniform Power Format (UPF) and dual power rails
    • Lowers overall system power by design
    • Configurable data buffering options to fine-tune performance/area trade-offs
    • Host supports SuperSpeed, High-Speed, Full-Speed, and Low-Speed operation
    Block Diagram -- SuperSpeed USB 3.0 Dual Role Device Controller, Configurable for SSIC and HSIC
  • SuperSpeed USB 3.0 Device Controller Supporting SSIC and HSIC
    • Supports SuperSpeed USB power savings modes, Uniform Power Format (UPF) and dual power rails
    • Lowers overall system power by design
    • Configurable data buffering options to fine-tune performance/area trade-offs
    • Host supports SuperSpeed, High-Speed, Full-Speed, and Low-Speed operation
    Block Diagram -- SuperSpeed USB 3.0 Device Controller Supporting SSIC and HSIC
  • HSIC PHY
    • Consumes <90mW during data transfer
    • Consumes <50uW when not transferring data
    • Uses standard chip digital and IO supplies
    • Low pin count
  • USB HSIC PHY - High Speed Inter-Chip IP Core
    • High-Speed 480Mbps data rate only
    • Source-synchronous seriel interface
    • No power consumed unless a transfer is in progress.
    • Maximum trace length of 10cm
    Block Diagram -- USB HSIC PHY - High Speed Inter-Chip IP Core
  • USB 2.0 Hi-Speed OTG Controller Subsystem w/AHB Interface Supporting HSIC (config. as Device only or Full Speed only)
    • Configuration options to maximize performance and minimize CPU interrupts
    • Flexible parameters enable easy integration into low and high-latency systems
    • Transfer- or transaction-based processing of USB data based on system requirements
    • Configurable data buffering options to fine-tune performance/ area trade-offs
    Block Diagram -- USB 2.0 Hi-Speed OTG Controller Subsystem w/AHB Interface Supporting HSIC (config. as Device only or Full Speed only)
  • Simulation VIP for USB
    • Configurations
    • Gen2x2, Gen1x2, Gen2x1, and Gen1x1
    • Supported DUT Models
    • Host, Device and PHY Model for USB2 or USB3
  • USB 1.0/1.1/2.0 Verification IP
    • USB 2.0
    • Compatible with USB 1.0, 1.1 and USB 2.0 specification
    • Supports Standard USB 2.0 interface, UTMI, UTMI+, ULPI and HSIC interfaces.
    • Standard DP/DM bus interface is supported.
    Block Diagram -- USB 1.0/1.1/2.0 Verification IP
  • eUSB Verification IP
    • eUSB
    • Compatible with Embedded USB2 (eUSB2) Physical Layer Supplement to the USB Revision 2.0 Specification Rev.1.1.
    • Fully compliant to the USB2.0 layer architecture with the following features:
    • Supports high-speed, full-speed, and low-speed operation.
    Block Diagram -- eUSB Verification IP
  • USB2.0/eUSB2.0 PHY & Controller
    • USB is the ubiquitous interconnect standard of choice for a wide range of computing and consumer applications
    • Innosilicon provides a comprehensive set of software drivers to support commonly used USB peripherals
    • In addition, our established USB ecosystem—comprising USB silicon suppliers, design IP houses, and verification and testing vendors—helps reduce development and production costs for USB host and peripheral manufacturers
    Block Diagram -- USB2.0/eUSB2.0 PHY & Controller
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