HSI IP
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17
IP
from 10 vendors
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10)
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MIPI HSI Controller - (High-Speed Synchronous Serial Interface)
- Compliant with MIPI HSI Specification version 1.0, and Physical Layer version 1.01.00
- Full Duplex High Speed Serial Interface between two peer devices
- 32 bit AHB, AXI or OCP Interface to CPU/Memory sub-system
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HW/SW interface foundation for design innovation
- Various Input Formats:
- CSRSpec Language
- SystemRDL
- IP-XACT
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IEEE 802.15.3c (60 GHz PHY) Multi-Gbit/s LDPC Decoder
- Compliant with IEEE 802.15.3c-2009 standard.
- Suitable for single carrier (SC) mode and high speed interface (HSI) mode.
- Support for all short LDPC codes (672 bits, code rates 1/2, 5/8, 3/4, 7/8).
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IEEE 802.15.3c Irregular LDPC(672,336), LDPC(672,504), LDPC(672,588) encoder and decoder
- Belief-propagation iterative decoding
- Pipeline design, 4 clocks perdecoding iteration
- Single clock synchronous design; registered inputs and outputs;
- Single-port memories only
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USB HSIC PHY - High Speed Inter-Chip IP Core
- High-Speed 480Mbps data rate only
- Source-synchronous seriel interface
- No power consumed unless a transfer is in progress.
- Maximum trace length of 10cm
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HSIC PHY
- Consumes <90mW during data transfer
- Consumes <50uW when not transferring data
- Uses standard chip digital and IO supplies
- Low pin count
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USB 2.0 EHCI Host Controller IP
- Compliance
- USB 2.0 Host
- Host Interface
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UFS 3.1 Host Controller compatible with M-PHY 4.1 and UniPro 1.8
- Seamless integration from PHY to Software
- Assured compliance across all components
- Single point of support
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UFS 4.0 Host Controller compatible with M-PHY 5.0 and UniPro 2.0
- JEDEC UFS 4.0, JEDEC UFS-HCI 4.0, MIPI M-PHY 5.0, MIPI UniPro 2.0
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USB 2.0 Host Controller
- Supports Low Speed (1.5 Mbps), Full Speed (12 Mbps) and High Speed (480 Mbps)
- Supports UTMI+Low Pin Interface (ULPI)
- Supports ULPI PHY low power mode and register access through software
- Supports 15 Bulk and 2 Interrupt Endpoints