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LPDDR2 Controller IP

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Compare 9 LPDDR2 Controller IP from 3 vendors (1 - 9)
  • LPDDR2 IP solution
    • Compatible with LPDDR2 up to 1066Mbps
    • AXI compliant multi-ports, and data width, FIFO depth, command queue depth configurable
    • DFI compliant interface between controller and PHY
    • Support ECC (error correcting code)
    Block Diagram -- LPDDR2 IP solution
  • LPDDR2 Synthesizable Transactor
    • Supports 100% of LPDDR2 protocol standard JESD209-2E and JESD209-2F
    • Supports all the LPDDR2 commands as per the specs
    • Supports up to 32GB device density
    • Supports following devices:
    Block Diagram -- LPDDR2 Synthesizable Transactor
  • LPDDR2 DFI Verification IP
    • Compliant with DFI version 2.1 or higher Specifications.
    • Supports LPDDR2 devices compliant with JEDEC LPDDR2 SDRAM Standard JESD209-2F.pdf and JESD209-2E.pdf
    • Supports for Read data-eye training
    • Supports for Read gate training
    Block Diagram -- LPDDR2 DFI Verification IP
  • LPDDR2 Controller IIP
    • Supports LPDDR2 protocol standard JESD209-2E and JESD209-2F Specification
    • Compliant with DFI version 2.1 or higher Specification.
    • Supports up to 16 AXI ports with data width upto 512 bits.
    • Supports controllable outstanding transactions for AXI write and read channels
    Block Diagram -- LPDDR2 Controller IIP
  • LPDDR Controller IIP
    • Supports LPDDR protocol standard and JESD209A-1 and JESD209B Specification
    • Compliant with DFI version 2.0 or higher Specification.
    • Supports up to 16 AXI ports with data width upto 512 bits.
    • Supports controllable outstanding transcations for AXI write and read channels
    Block Diagram -- LPDDR Controller IIP
  • LPDDR2 Assertion IP
    • Specification Compliance
    • Supports LPDDR2 memory devices from all leading vendors.
    • Supports 100% of LPDDR2 protocol standard JESD209-2E and JESD209-2F.
    • Supports all the LPDDR2 commands as per the specs.
    Block Diagram -- LPDDR2 Assertion IP
  • LPDDR2 DFI Assertion IP
    • Specification Compliance
    • Compliant with DFI version 2.1 or higher Specifications.
    • Supports LPDDR2 devices compliant with JEDEC LPDDR2 SDRAM Standard JESD209-2F.pdf and JESD209-2E.pdf.
    • Supports for Read data-eye training.
    Block Diagram -- LPDDR2 DFI Assertion IP
  • LPDDR DFI Assertion IP
    • Specification Compliance
    • Compliant with DFI version 2.0 or higher Specifications.
    • Supports LPDDR devices compliant with JEDEC LPDDR SDRAM Standard JESD209A-1.pdf and JESD209B.pdf.
    • Supports all Interface Groups.
    Block Diagram -- LPDDR DFI Assertion IP
  • Universal Multiport Memory Controller - LPDDR 3/2 Controller
    • Compliant with AXI V4.0 specification
    • Compliant with DFI 3.1 specification
    • Compliant with JEDEC LPDDR2 and LPDDR3 standards
    • Support for 8, 16, 32 SDRAM bus width, for a total memory data path width up to 64 bits
    Block Diagram -- Universal Multiport Memory Controller - LPDDR 3/2 Controller
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