USB 3.2 PHY IP
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USB 3.2 PHY IP
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11
USB 3.2 PHY IP
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USB3.2 Gen2 x2-lane, Dual-Role PHY, TSMC N6, 1.8V, N/S orientation, type-C
- Worldwide smallest USB 3.2 Gen2 PHY IP (e.g. IP size @28HPC+ is smaller than 0.7mm²)
- Fully compliant with Universal Serial Bus (USB) 3.2 Gen2 and 2.0 electrical specifications
- Supports clock inputs from 10/12/19.2/24/25/27/30/40MHz crystal oscillator and external clock sources from the core
- Supports 3-Tap FIR Equalization for TX and CTLE+1-Tap DFE for RX
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USB 3.2 Gen2x2 with PIPE 4.3 and USB2.0 with UTMI+ interface
- Fully compliant USB 3.2 Gen2x2 with PIPE 4.3 and USB2.0 with UTMI+ interface
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USB 3.2/ PCIe 3.1/ SATA 3.2 Combo PHY IP, Silicon Proven in UMC 28HPC
- Compliant with PCIe 3.1 Base Specification
- Compliant with Universal Serial Bus 3.2 Specification
- Compliant with Universal Serial Bus 2.0 Specification
- Compliant with UTMI 1.05 Specification
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USB-C 3.2 SS/SSP PHY in Type-C in TSMC (N7, N6, N5, N3E)
- Supports 20Gbps, 10Gbps, and 5Gbps data rates
- Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
- x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
- Low active and standby power
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USB-C 3.2 SS/SSP PHY in Type-C in Samsung (SF4X, SF4E, SF2)
- Supports 20Gbps, 10Gbps, and 5Gbps data rates
- Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
- x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
- Low active and standby power
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USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm,6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
- USB 3.2 Gen2
- 1. Worldwide smallest USB 3.2 Gen2 PHY IP (e.g. IP size @28HPC+ is smaller than 0.7mm²)
- 2. Fully compliant with Universal Serial Bus (USB) 3.2 Gen2 and 2.0 electrical specifications
- 3. Supports clock inputs from 10/12/19.2/24/25/27/30/40MHz crystal oscillator and external clock sources from the core