USB 3.1 PHY IP for TSMC
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USB 3.1 PHY IP
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13
USB 3.1 PHY IP
for TSMC
from 3 vendors
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10)
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Complete USB Type-C Power Delivery PHY, RTL, and Software
- USB PD 3.1 compliant.
- 8 bit register interface for a low speed processor, or optional I2C interface.
- Integrated Chapter 6 protocol reduces required MPU response time to 10mS.
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USB-C 3.1 DP/TX PHY ebdaux in TSMC (N5, N3E)
- Lowest risk: Based on proven USB 3.0 controller shipped in 100s of millions of units
- Lowest power: Extend battery life in mobile devices (USB power saving modes, Uniform Power Format, hibernation option with dual power rails)
- Configurable data buffering options to optimize performance vs area
- Supports all USB speed modes
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USB 3.1 PHY (10G/5G) inTSMC (16nm, 12nm, N7, N6, N5,N3E)
- Lowest risk: Based on proven USB 3.0 controller shipped in 100s of millions of units
- Lowest power: Extend battery life in mobile devices (USB power saving modes, Uniform Power Format, hibernation option with dual power rails)
- Configurable data buffering options to optimize performance vs area
- Supports all USB speed modes
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USB-C 3.1 SS/SSP PHY in Type-C in TSMC (16nm, 12nm, N7, N6, N5, N5A)
- Lowest risk: Based on proven USB 3.0 controller shipped in 100s of millions of units
- Lowest power: Extend battery life in mobile devices (USB power saving modes, Uniform Power Format, hibernation option with dual power rails)
- Configurable data buffering options to optimize performance vs area
- Supports all USB speed modes
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USB-C 3.1/DP TX PHY in TSMC (16nm, 12nm, N7, N6)
- Lowest risk: Based on proven USB 3.0 controller shipped in 100s of millions of units
- Lowest power: Extend battery life in mobile devices (USB power saving modes, Uniform Power Format, hibernation option with dual power rails)
- Configurable data buffering options to optimize performance vs area
- Supports all USB speed modes
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Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 65GP process
- - Parallel data widths of 8bits and 16bits
- - QUAD configuration (4TX and 4RX), Single lane configuration (1TX and 1RX)
- - Support signal loss and receiver detection using programmable multi-tap
- - Support 1m cable
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Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 55LP process
- - Parallel data widths of 8bits and 16bits
- - QUAD configuration (4TX and 4RX), Single lane configuration (1TX and 1RX)
- - Support signal loss and receiver detection using programmable multi-tap
- - Support 1m cable
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Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in GF 28SLP process
- - Parallel data widths of 8bits and 16bits
- - QUAD configuration (4TX and 4RX), Single lane configuration (1TX and 1RX)
- - Support signal loss and receiver detection using programmable multi-tap
- - Support 1m cable
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Single Lane and Quad Lane 5Gbps USB3.1 PHY IP in TSMC 28HPC process
- - Parallel data widths of 8bits and 16bits
- - QUAD configuration (4TX and 4RX), Single lane configuration (1TX and 1RX)
- - Support signal loss and receiver detection using programmable multi-tap
- - Support 1m cable
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Single Lane and Quad Lane 10Gbps USB3.1 PHY IP in TSMC 65GP process
- - Parallel data widths of 8bits and 16bits
- - QUAD configuration (4TX and 4RX), Single lane configuration (1TX and 1RX)
- - Support signal loss and receiver detection using programmable multi-tap
- - Support 1m cable