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USB 3.1 PHY IP for TSMC

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Compare 35 USB 3.1 PHY IP for TSMC from 3 vendors (1 - 10)
  • Complete USB Type-C Power Delivery PHY, RTL, and Software
    • USB PD 3.1 compliant.
    • 8 bit register interface for a low speed processor, or optional I2C interface.
    • Integrated Chapter 6 protocol reduces required MPU response time to 10mS.
    Block Diagram -- Complete USB Type-C Power Delivery PHY, RTL, and Software
  • USB-C 3.1/DP TX PHY for TSMC N7, North/South Poly Orientation for Automotive AEC-Q100 Grade 2
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB-C 3.1/DP TX PHY for TSMC N7, North/South Poly Orientation for Automotive AEC-Q100 Grade 2
  • USB-C 3.1 SS/SSP PHY, Type-C - TSMC N5A 1.2V, North/South Poly Orientation for Automotive AEC-Q100 Grade 2
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB-C 3.1 SS/SSP PHY, Type-C - TSMC N5A 1.2V, North/South Poly Orientation for Automotive AEC-Q100 Grade 2
  • USB-C 3.1 SS/SSP PHY, Type-C - TSMC N5, North/South Poly Orientation
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB-C 3.1 SS/SSP PHY, Type-C - TSMC N5, North/South Poly Orientation
  • USB 3.1 PHY (10G/5G) - TSMC N5 x1 OTG, North/South Poly Orientation
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB 3.1 PHY (10G/5G) - TSMC N5 x1 OTG, North/South Poly Orientation
  • USB 3.1 PHY (10G/5G) - TSMC N3P X1 OTG, North/South Poly Orientation
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB 3.1 PHY (10G/5G) - TSMC N3P X1 OTG, North/South Poly Orientation
  • USB 3.1 PHY (10G/5G) - TSMC N3A x1 OTG, North/South Poly Orientation for Automotive AEC-Q100 Grade 2
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB 3.1 PHY (10G/5G) - TSMC N3A x1 OTG, North/South Poly Orientation for Automotive AEC-Q100 Grade 2
  • USB-C 3.1 SS/SSP PHY, Type-C - TSMC 7FF x1, North/South Poly Orientation
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB-C 3.1 SS/SSP PHY, Type-C - TSMC 7FF x1, North/South Poly Orientation
  • USB 3.1 PHY (10G/5G) - TSMC 7FF x1 OTG, North/South Poly Orientation
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB 3.1 PHY (10G/5G) - TSMC 7FF x1 OTG, North/South Poly Orientation
  • USB-C 3.1 SS/SSP PHY, Type-C - TSMC 6FF x1, North/South Poly Orientation
    • Part of a complete IP solution including xHCI host and device controllers, PHYs, verification IP, 1 IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C 3.1 PHY IP supports USB Type-C specification
    • Supports the SuperSpeedPlus (10 Gbps) and SuperSpeed (5 Gbps) speed modes
    Block Diagram -- USB-C 3.1 SS/SSP PHY, Type-C - TSMC 6FF x1, North/South Poly Orientation
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