RapidIO IP for TSMC
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RapidIO IP
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RapidIO IP
for TSMC
from 2 vendors
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A 130nm Wirebond IO library with 3.3V GPIO, LVDS TX & RX, 3.3V I2C open-drain, analog cell and OTP program cell
- GPIO:
- I2C / SMBUS Open-Drain I/O:
- LVDS
- ANALOG
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A 65nm Wirebond IO library with 1-3.3V GPIO, 3.3V pulse-width modulation cell, I2C & SVID open-drain, 3.3V & 5V analog and OTP program cell
- GPIO:
- I2C / SVID Open-Drain I/O:
- ANALOG
- OTP Programming Cell
-
RapidIO 2.0 PHY & Controller
- One to Four independent 1.25/2.5/3.125Gbps per ports
- Features as per RapidIO Specification revision v2.2
- Precision low jitter master PLL and CDR loop
- Supporting a 10 bit SerDes interface