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MIPI IP for SMIC

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Compare 42 MIPI IP for SMIC from 7 vendors (1 - 10)
  • MIPI D-PHY DSI RX (Receiver) in SMIC 130nm
    • SMIC 130nm
    • Consists of 1 Clock lane and 4 Data lanes
    • Supporting the MIPI Standard 1.1 for D-PHY
    Block Diagram -- MIPI D-PHY DSI RX (Receiver) in SMIC 130nm
  • MIPI M-PHY in SMIC 90LL
    • Supports MIPI Standard for M-PHY v3.0.
    • Dual-simplex point-to-point interface with ultra low voltage differential signaling
    Block Diagram -- MIPI M-PHY in SMIC 90LL
  • MIPI M-PHY in SMIC 130nm
    • Complies with MIPI Standard for M-PHY v3.0
    • Slew-rate control for EMI reduction
    • Supports HS modes GEAR 1-3
    Block Diagram -- MIPI M-PHY in SMIC 130nm
  • MIPI M-PHY DigRF Compliant IP
    • Complies with MIPI Standard for M-PHY, Draft Specification v0.90.00- r02 and DigRF v4 V1.10.00.0.04
    • Dual-simplex point-to-point interface with ultra low voltage differential signaling
    • Slew-rate control for EMI reduction
    • Supports HS mode (GEAR 1-2, A & B)
    Block Diagram -- MIPI M-PHY DigRF Compliant IP
  • MIPI M-PHY Compliant (HS-G2) IP
    • Complies with MIPI Standard for M-PHY, Draft Specification v0.90.
    • Dual-simplex point-to-point interface with ultra low voltage differential signaling
    • Slew-rate control for EMI reduction
    • Supports all HS modes (GEAR 1-2)
    Block Diagram -- MIPI M-PHY Compliant (HS-G2) IP
  • MIPI D-PHY CSI-2 RX (Receiver) IP
    • Consists of 1 Clock lane and 2 Data lanes
    • Complies with MIPI Standard 1.0 for D-PHY
    • Supports both high speed and low-power modes
    • 80 Mbps to 1Gbps data rate in high speed mode
    Block Diagram -- MIPI D-PHY CSI-2 RX (Receiver) IP
  • MIPI PLL
    • All output programmable dividers produce 50% duty cycle for both even and odd divisors
    • High performance, highly programmable MIPI Pixel PLL
    • Digital CMOS process
    • Low power dissipation
    Block Diagram -- MIPI PLL
  • MIPI D-PHY Universal IP
    • Complies with MIPI Standard for D-PHY V1.0
    • Point-to-point differential interface supporting multiple data lanes and a clock lane
    • Supports both high speed and low-power modes
    • Data lanes support both bidirectional and unidirectional modes
    Block Diagram -- MIPI D-PHY Universal IP
  • MIPI D-PHY Tx-Only 4 Lanes in SMIC (28nm)
    • Compliant with the MIPI D-PHY specification
    • Fully verified hard macro
    • Up to 2.5 Gb/s per lane
    • Aggregate throughput up to 10 Gb/s in 4 data lanes
  • MIPI D-PHY Rx-Only 4 Lanes in SMIC (40nm, 28nm)
    • Compliant with the MIPI D-PHY specification
    • Fully verified hard macro
    • Up to 2.5 Gb/s per lane
    • Aggregate throughput up to 10 Gb/s in 4 data lanes
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