Chiplet and D2D IP for Samsung

Compare 15 Chiplet and D2D IP for Samsung from 5 vendors (1 - 10)

2-16Gbps Multi-Protocol IO Supporting BOW, OHBI and UCIe
- High Bandwidth Density and Data Rates
- Package Configurability
- Energy Efficiency
- Fully Integrated Solution
UCIe-S PHY for Standard Package (x16) in SS SF4X, North/South Orientation
- Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
- Compliant with the latest UCIe specification
- Integrated signal integrity monitors and comprehensive test and repair features
- Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
UCIe-A PHY for Advanced Package (x64) in SS SF4X, North/South Orientation with 8collumn module configuration
- Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
- Compliant with the latest UCIe specification
- Integrated signal integrity monitors and comprehensive test and repair features
- Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
UCIe-A (Gen2) PHY for Advanced Package (x64) in SS SF4X, North/South Orientation
- Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
- Compliant with the latest UCIe specification
- Integrated signal integrity monitors and comprehensive test and repair features
- Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
UCIe-S PHY for Standard Package (x16) in SS SF5A, North/South Orientation
- Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
- Compliant with the latest UCIe specification
- Integrated signal integrity monitors and comprehensive test and repair features
- Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
UCIe-S PHY for Standard Package (x16) in Samsung (SF5A, SF4X, SF2)
- Data rates up to 16Gbps per pin
- Self-contained hard macro
- Self-calibrating and training
- Side band channel for initialization and parameter exchange
Chiplet Interconnect - Die-to-die interconnect IP solutions for advanced and standard packaging applications
- High data rate of 2–24 Gb/s
- Very low power of < 0.375 pJ/bit @ 2–16 Gb/s 0.5-V VDDQ
- Very low latency of < 2 ns PHY-to-PHY
- Support for 2:1, 4:1, 8:1, 12:1 and 16:1 serialization and deserialization ratios
Die-2-die interfaces for chiplets
- Analog I/Os
- ESD Power protection
- Ground pads
INNOLINK-C Controller
- General Features
- DFI Features
INNOLINK-C PHY
- LPDDR5 like interface with IO voltage 0.4V and core power supply 0.9V
- 12Gbps for maximum IO speed in HLMC 28nm process
- Default 64-bit DQ Tx+ 64-bit DQ Rx per module, module number can be 1/2/4/8/16 or more
- Burst data, forward clock, no CDR