INNOLINK-C PHY

Overview

Innosilicon can provide different Die-to-Die and Chip-to-Chip solutions for customer according to package types. The followings are Innosilicon Die-to-Die and Chip-to-Chip IP family:

  •  Innolink-A, SerDes-based, up to 32 or 56Gbps/pair, long-reach, chip to chip or board to board connection.
  •  Innolink-B, GDDR-like, single-ended, up to 24Gbps/pin, typical MCM or short PCB application, with bump pitch of 100um~150um. Innolink-B is compatible with UCIe standard package version at physical layer, and Innosilicon is developing UCIe adapter layer and protocol layer. If customer don’t need the compatibility with third-party chiplet connection, Innosilicon can provide silicon proven Innolink controller solution. Please find detailed information at Innolink Controller databook.
  •  Innolink-C, GDDR-like and LPDDR5-like, optimized for silicon interposer, super small IO and 0.4V IO voltage, up to 24Gbps/pin, with bump pitch of 40um~100um. Innolink-C is compatible with UCIe advanced package version at physical layer, and Innosilicon is developing UCIe adapter layer and protocol layer. If customer don’t need the compatibility with third-party chiplet connection, Innosilicon can provide silicon proven Innolink controller solution. Please find detail information at Innolink Controller databook.

Innosilicon can provide the PHY solution, as well as PHY + Controller solution. The PHY is provided as a full harden IP, while Controller is provided as a soft IP. This databook is for Innolink-C PHY solution with DFI-like interface.

INNOLINK-C is designed to perform high speed data communication between dies. The physical implementation methodology of INNOLINK-C is a DDR-like interface, which use single ended signal for IO interface, forward clock is used for Rx data sampling.

For this process, The Innolink-C speed up to 12Gbps per DQ.

By default, Innolink-C adopts 64-bit Tx DQs and 64-bit Rx DQs per module, when each DQ runs at 12Gbps with two modules equipped (64-bit Tx + 64-bit Rx) * 2, it provides a total bandwidth of 1.536Tbps for Tx and 1.536Tbps for Rx. Innolink-C can be configured to 1/2/4/8/16/32 modules, and this datasheet is an example of 1 module configuration (64-bit Tx + 64-bit Rx).

Innolink can be easily integrated with Innolink controller, and IO input/output direction can be software defined.

Key Features

  • LPDDR5 like interface with IO voltage 0.4V and core power supply 0.9V
  • 12Gbps for maximum IO speed in HLMC 28nm process
  • Default 64-bit DQ Tx+ 64-bit DQ Rx per module, module number can be 1/2/4/8/16 or more
  • Burst data, forward clock, no CDR
  • Minimum bump pitch is 55um
  • Support Driver strength and ODT strength adjustable
  • IO is bi-directional, software can define IO direction
  • Support data remap for easy connection
  • Support PHY independent handshake and training
  • Support per-bit delay and vref 2D training
  • Support on die eye opening read out (on die scope)
  • Automatic VT tracking and compensation
  • DFI data like interface to core logic
  • BIST logic integrated, two loop back modes
  • PLL integrated to generate high speed clocks
  • Sideband interface for low speed communication between both PHYs (optional)
  • Support redundant signals for repair, support side band signals
  • PHY independent Tx and Rx training, Support per bit training
  • All signal IOs are bidirectional, software can define input or output (optional)

Benefits

  • Available in any 40nm or below technology nodes
  • Significantly lower cost, shorter time to market, lower supply risks for OEMs and simpler architectural partitioning than the monolithic silicon integration
  • Offers leading performance, power, and area per terabit
  • Flexible configuration with support for silicon interposer, package substrate and PCB options
  • Customizable synthesis for any FPGAs and ASICs
  • Full support from IP delivery to production

Applications

  • High performance computing (HPC) applications
  • Next-generation data center
  • Networking
  • 5G communication
  • Artificial intelligence / machine learning (AI/ML) applications

Deliverables

  • Databook and physical implementation guides
  • Netlist (Spice format for LVS)
  • Library Exchange Format (LEF)
  • Verilog Models
  • GDSII to Foundry IP Merge
  • Module integration guidelines
  • Silicon validation report (when available)
  • Evaluation board (when available)

Technical Specifications

Foundry, Node
TSMC12/7/6/5/4nm, SMIC 28/14nm, HLMC 28nm, Samsung 5nm
SMIC
In Production: 14nm , 28nm
Silicon Proven: 14nm , 28nm
Samsung
In Production: 5nm
Pre-Silicon: 14nm
Silicon Proven: 5nm
TSMC
In Production: 4nm , 5nm , 6nm , 7nm , 12nm
Silicon Proven: 4nm , 5nm , 6nm , 7nm , 12nm
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Semiconductor IP