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DDR5 PHY IP for GLOBALFOUNDRIES

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Compare 11 DDR5 PHY IP for GLOBALFOUNDRIES from 3 vendors (1 - 10)
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  • 12nm
  • DDR PHY
    • DDR5/4/3 training with write-leveling and data-eye training
    • Optional clock gating available for low-power control
    • Internal and external datapath loop-back modes
    • I/O pads with impedance calibration logic and data retention capability
    • Programmable per-bit (PVT compensated) deskew on read and write datapaths
    • RX and TX equalization for heavily loaded systems
    Block Diagram -- DDR PHY
  • DDR5/4 PHY - GF 12LP+
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs
    • High-performance DDR PHY supporting data rates up to 8400 Mbps
    • PHY independent, firmware-based training using an embedded calibration processor
    • Supports up to 4 trained states/ frequencies with <3μs switching time
    Block Diagram -- DDR5/4 PHY - GF 12LP+
  • LPDDR4X multiPHY Plus in GF (12nm)
    • Low latency, small area, low power
    • Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps
    • Maximum data rate is process technology dependent
    • Compatible with JEDEC standard DDR4 SDRAMs up to 3,200 Mbps
  • DDR5/4 PHY in GF (12nm)
    • Low latency, small area, low power
    • Compatible with JEDEC standard DDR5 SDRAMs up to 8400 Mbps
    • Compatible with JEDEC standard DDR4 SDRAMs up to 3200 Mbps
    • DFI 5.0 compliant interface to the memory controller
  • DDR4 Multi-modal PHY - GLOBALFOUNDRIES 12nm
    • PLL-based clocking with internal clock alignment to the parallel clock on the memory controller interface
    • Autonomous initialization
    • Support for x72 bit channel
    • Support for multiple DRAM widths (x4, x8, x16, x32)
  • DDR4 PHY - GLOBALFOUNDRIES 12nm
    • PLL-based clocking with internal clock alignment to the parallel clock on the memory controller interface
    • Autonomous initialization
    • Support for x72 bit channel
    • Support for multiple DRAM widths (x4, x8, x16, x32)
  • DDR5/4 Combo PHY & Controller
    • DDR5 and DDR4 modes & signaling, rates from 20Mbps up to 5200Mbps (DDR5) and 3200Mbps (DDR4), respectively
    • x16/x32/x64/x72/x80 data path interface extendable, support UDIMM, RDIMM and LRDIMM
    • 1.1V/1.2V JEDEC IO standard, supporting 1.1V POD_11 and 1.2V POD_12 I/Os
    • Support DDR5 dual channel mode, dual 32bit data +8bit ECC
  • DDR4/LPDDR4/4X/3 Combo PHY & Controller
    • DDR4 and LPDDR4/4X/3 modes & signaling, rates from 20Mbps up to 3200Mbps (DDR4), 4266Mbps (LPDDR4/4X) and 2133Mbps (LPDDR3), respectively
    • x16/x32/x64 data path interface extendable
    • 1.2V/1.1V JEDEC IO standard, support 1.2V POD_12 I/Os and 1.1V LVSTL I/Os
    • Optional limited swing to VDDQ/3 in LPDDR4 mode
  • DDR4/LPDDR4/3 Combo PHY & Controller
    • DDR4 and LPDDR4/3 modes & signaling, rates from 20Mbps up to 2667Mbps (DDR4/LPDDR4) and 2133Mbps (LPDDR3), respectively
    • x16/x32/x64 data path interface extendable
    • 1.2V/1.1V JEDEC IO standard, support 1.2V POD_12 I/Os and 1.1V LVSTL I/Os
    • Multiple drive strengths adjustable
  • DDR4/3/LPDDR4X/4/3 Combo PHY & Controller
    • DDR4/3 and LPDDR4/4X/3 modes & signaling, rates from 20Mbps up to 2667Mbps (DDR4/LPDDR4/4X) and 2133Mbps (DDR3/LPDDR3), respectively
    • x16/x32 data path interface extendable
    • 1.2V/1.1V/1.5V JEDEC IO standard, support 1.5V SSTL, 1.2V POD_12 I/Os and 1.1V LVSTL I/Os
    • Optional limited swing to VDDQ/3 in LPDDR4 mode
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