DDR5/4 Combo PHY & Controller

Overview

The INNOSILICON DDR IPTM Mixed-Signal DDR5/4 Combo PHY s provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for low power and high speed applications with robust timing and small silicon area. It supports all JEDEC DDR5/4 SDRAM components in the market. The PHY components contain DDR specialized functional and utility high performance I/Os, critical timing synchronization module (TSM) and a low power/jitter DLLs with programmable fine-grain control for any SDRAM interface.
Note that all INNOSILICON PHY is pre-assembled with.lib, LEF and GDS so that it is very easy to integrate the PHY with any existing SoC floor plan. DDRn bus width can be from 4 bit to 72 bit or more. INNOSILICON is happy to pre-assemble each PHY for our customer so that integration becomes extremely easy.
The combo PHY solution includes DDRn controller and PHY, supporting DDR4 / LPDDR4 /LPDDR3. With configurable timing and driving strength parameters to interface to the wide variety of SDRAMs, the PHY is very flexible with advanced command capability to increase SDRAM operation efficiency.

Key Features

DDR5 and DDR4 modes & signaling, rates from 20Mbps up to 5200Mbps (DDR5) and 3200Mbps (DDR4), respectively
x16/x32/x64/x72/x80 data path interface extendable, support UDIMM, RDIMM and LRDIMM
1.1V/1.2V JEDEC IO standard, supporting 1.1V POD_11 and 1.2V POD_12 I/Os
Support DDR5 dual channel mode, dual 32bit data +8bit ECC
Support CA training, CS training, and write leveling training modes
Support Write FFE and Read DFE equalization
Independent read and write timing adjustments with auto calibration, dynamic V&T tracking
Both Read and Write Per bit deskew support
Support over 10 training modes for stability working
Support Maximum 4 frequency points fast change
Supports point to point memory sub systems and multi-rank
PVT compensation and timing calibration for all corner reliability
At speed BIST, scan insertion
Various power-down modes for low power including self-refresh support
APB Port register access interface
Implemented using 0.75V RVT&LVT core devices and 1.8V gate oxide IO devices

Benefits

Fully pre-assemble design, Drop-in hard macro to ease integration and speed time to market
Zero risk with robust ESD architecture
Maintains self-refresh I/O drive state during VDD power down
Extensive EDA tool support for various design automation flows
DFI5.0/4.0 compliant memory controller interface
Takes full advantage of process power savings and speed capability
Best in class low noise design to ensure best timing margin and signal integrity
DFT functions to reduce test time and ensure high test coverage
Several programmable PHY operating modes through simple register interface
Per Bit De-skew to improve composite data eye during read cycles at high speed

Deliverables

Verilog models
LEF
Place-and-route abstracts
GDSII files
LVS netlists
Optional extracted HSPICE netlist for I/Os
Data book, Application notes
Silicon validation and ESD testing results
Optional PCB reference design and Package Electrical Model
DocumentationL: Documentation for the Innosilicon PHY will be delivered as part of the access package.

Technical Specifications

Foundry, Node

TSMC 12/7/6/5/4/3nm,Samsung 28/8/5/4nm, SMIC 14/12nm, HLMC 28nm, GF22/12nm

Maturity

Silicon Proven

Availability

Available

GLOBALFOUNDRIES

In Production: 12nm , 22nm
Silicon Proven: 12nm , 22nm

SMIC

In Production: 14nm
Silicon Proven: 14nm

Samsung

In Production: 4nm , 5nm , 8nm , 28nm LPP
Silicon Proven: 4nm , 5nm , 8nm , 28nm LPP

TSMC

In Production: 3nm , 4nm , 5nm , 6nm , 7nm , 12nm
Silicon Proven: 3nm , 4nm , 5nm , 6nm , 7nm , 12nm

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