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DDR5 PHY IP for GLOBALFOUNDRIES

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Compare 18 DDR5 PHY IP for GLOBALFOUNDRIES from 4 vendors (1 - 10)
  • LPDDR4X multiPHY Plus in GF (12nm)
    • Low latency, small area, low power
    • Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps
    • Maximum data rate is process technology dependent
    • Compatible with JEDEC standard DDR4 SDRAMs up to 3,200 Mbps
  • LPDDR4X multiPHY in GF (14nm)
    • Low latency, small area, low power
    • Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps
    • Maximum data rate is process technology dependent
    • Compatible with JEDEC standard DDR4 SDRAMs up to 3,200 Mbps
  • LPDDR4 multiPHY V2 in GF (22nm) for Automotive
    • Low latency, small area, low power
    • Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps
    • Maximum data rate is process technology dependent
    • Compatible with JEDEC standard DDR4 SDRAMs up to 3,200 Mbps
  • LPDDR4 multiPHY V2 in GF (22nm)
    • Low latency, small area, low power
    • Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps
    • Maximum data rate is process technology dependent
    • Compatible with JEDEC standard DDR4 SDRAMs up to 3,200 Mbps
  • DDR5/4 PHY in GF (12nm)
    • Low latency, small area, low power
    • Compatible with JEDEC standard DDR5 SDRAMs up to 8400 Mbps
    • Compatible with JEDEC standard DDR4 SDRAMs up to 3200 Mbps
    • DFI 5.0 compliant interface to the memory controller
  • DDR4 Multi-modal PHY - GLOBALFOUNDRIES 12nm
    • PLL-based clocking with internal clock alignment to the parallel clock on the memory controller interface
    • Autonomous initialization
    • Support for x72 bit channel
    • Support for multiple DRAM widths (x4, x8, x16, x32)
  • DDR3 PHY - GLOBALFOUNDRIES 12nm
    • PLL-based clocking with internal clock alignment to the parallel clock on the memory controller interface
    • Autonomous initialization
    • Support for x72 bit channel
    • Support for multiple DRAM widths (x4, x8, x16, x32)
  • DDR4 PHY - GLOBALFOUNDRIES 12nm
    • PLL-based clocking with internal clock alignment to the parallel clock on the memory controller interface
    • Autonomous initialization
    • Support for x72 bit channel
    • Support for multiple DRAM widths (x4, x8, x16, x32)
  • PSRAM PHY
    • PSRAM modes & signaling, rates from 200Mbps up to 1600Mbps
    • x8 data path interface
    • 2.5V I/O devices
    • Multiple drive strengths adjustable
  • DDR5/4 Combo PHY & Controller
    • DDR5 and DDR4 modes & signaling, rates from 20Mbps up to 5200Mbps (DDR5) and 3200Mbps (DDR4), respectively
    • x16/x32/x64/x72/x80 data path interface extendable, support UDIMM, RDIMM and LRDIMM
    • 1.1V/1.2V JEDEC IO standard, supporting 1.1V POD_11 and 1.2V POD_12 I/Os
    • Support DDR5 dual channel mode, dual 32bit data +8bit ECC
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