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DDR IP for GLOBALFOUNDRIES

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Compare 22 DDR IP for GLOBALFOUNDRIES from 5 vendors (1 - 10)
  • LPDDR5T / LPDDR5X / LPDDR5 Controller
    • Support for all LPDDR5T/5X/5 devices
    • Bank management logic monitors status of each bank
    • Queue-based user interface with reordering scheduler
  • LPDDR5/4/4X PHY in GF (12nm)
    • Low latency, small area, low power
    • Compatible with JEDEC standard LPDDR5 SDRAMs up to 6400 Mbps
    • Compatible with JEDEC standard LPDDR4 and LPDDR4X SDRAMs up to 4267 Mbps
    • DFI 5.0 compliant interface to the memory controller
  • LPDDR4X multiPHY Plus in GF (12nm)
    • Low latency, small area, low power
    • Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps
    • Maximum data rate is process technology dependent
    • Compatible with JEDEC standard DDR4 SDRAMs up to 3,200 Mbps
  • LPDDR4X multiPHY in GF (14nm)
    • Low latency, small area, low power
    • Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps
    • Maximum data rate is process technology dependent
    • Compatible with JEDEC standard DDR4 SDRAMs up to 3,200 Mbps
  • LPDDR4 multiPHY V2 in GF (22nm) for Automotive
    • Low latency, small area, low power
    • Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps
    • Maximum data rate is process technology dependent
    • Compatible with JEDEC standard DDR4 SDRAMs up to 3,200 Mbps
  • LPDDR4 multiPHY V2 in GF (22nm)
    • Low latency, small area, low power
    • Compatible with JEDEC standard LPDDR4 SDRAMs up to 4,267 Mbps
    • Maximum data rate is process technology dependent
    • Compatible with JEDEC standard DDR4 SDRAMs up to 3,200 Mbps
  • DDR5/4 PHY in GF (12nm)
    • Low latency, small area, low power
    • Compatible with JEDEC standard DDR5 SDRAMs up to 8400 Mbps
    • Compatible with JEDEC standard DDR4 SDRAMs up to 3200 Mbps
    • DFI 5.0 compliant interface to the memory controller
  • DDR4 Multi-modal PHY - GLOBALFOUNDRIES 12nm
    • PLL-based clocking with internal clock alignment to the parallel clock on the memory controller interface
    • Autonomous initialization
    • Support for x72 bit channel
    • Support for multiple DRAM widths (x4, x8, x16, x32)
  • DDR3 PHY - GLOBALFOUNDRIES 12nm
    • PLL-based clocking with internal clock alignment to the parallel clock on the memory controller interface
    • Autonomous initialization
    • Support for x72 bit channel
    • Support for multiple DRAM widths (x4, x8, x16, x32)
  • DDR4 PHY - GLOBALFOUNDRIES 12nm
    • PLL-based clocking with internal clock alignment to the parallel clock on the memory controller interface
    • Autonomous initialization
    • Support for x72 bit channel
    • Support for multiple DRAM widths (x4, x8, x16, x32)
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