USB IP for GLOBALFOUNDRIES

Compare 10 USB IP for GLOBALFOUNDRIES from 2 vendors (1 - 10)

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12nm

USB 2.0 femtoPHY - GF 12LPP18 x1, OTG, North/South (vertical) poly orientation
- Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
- Supports the USB 2.0 protocol and data rate (480 Mbps)
- Supports the USB Type-C specification
- USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
USB 2.0 femtoPHY - GF 12LP x1, OTG, North/South (vertical) poly orientation
- Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
- Supports the USB 2.0 protocol and data rate (480 Mbps)
- Supports the USB Type-C specification
- USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
USB-C 3.2 DP/TX PHY for GF 12LP+, North/South poly orientation
- USB-IF certified Synopsys USB 3.2 solution
- VESA certified Synopsys DisplayPort 1.4 Tx solution
- Industry’s only USB Type-C IP solution consisting of USB-C 3.2/DisplayPort 1.4 TX PHYs, USB-C 3.2/DisplayPort 1.4 TX controllers with HDCP 2.2 and HDCP 2.2 content protection, verification IP, and IP subsystems
- Solution supports USB Type-C, SuperSpeed USB 3.2 at 20 Gbps, SuperSpeed USB 3.1 at 10 Gbps, SuperSpeed USB 3.0 at 5 Gbps and High-Speed USB (USB 2.0) as well as DisplayPort 1.4 TX supporting RBR, HBR1, HBR2 and HBR3 bitrates
USB-C 3.2 DP/TX PHY in GF (12nm)
USB 2.0 femtoPHY in GF (28nm, 22nm, 12nm)
- Complete mixed-signal physical layer for single-chip USB 2.0 Host, Device, and Dual Role applications Small PHY macro area: as small as 0.20 mm2
- Low power: as low as 50mW (during high-speed packet transmission)
- Advanced power management features including support for power supply gating, supply scaling, ultra-low standby current support, and power management unit (PMU) interrupt support
- Supports USB 2.0 ID-pin detection and OTG Voltage Detectors
USB 3.0 femtoPHY in GF (28nm, 12nm)
- Complete mixed-signal physical layer for USB 3.0 applications
- Includes all circuitry needed for operation at all USB speeds (SuperSpeed, High-Speed, FullSpeed, Low-Speed)
- USB-C 3.0 femtoPHY supports Type-C reversible connectors
- Optimized PHY area (<0.5mm2 for USB 3.0, <0.8mm2 for USB-C 3.0)
USB3.2 PHY
- Reference Clock:
- Internal PLL:
- Data Transmit:
- Data Receive:
USB2.0 PHY & Controller
- Compliant with USB Specification Revision 2.0, 1.1
- Configurable 8-bit or 16-bit UTMI interface compliant with UTMI+ Specification Level 3 Revision 1.0
- Supports 480Mbps (HS), 12Mbps (FS) and 1.5Mbps (LS) serial data transmission
- Supports low latency hub mode with 40-bit time round trip delay
PCIe 3.0/3.1/USB3.0/SATA3 Combo PHY
- Standard PHY interface enables multiple IP sources for PCI Express Logical Layer and provides a target interface for PCI Express PHY vendors.
- Supports 2.5Gb/s only or 2.5Gb/s,5.0Gb/s and 8.0Gb/s serial data transmission rate
- Utilizes 8-bit, 16-bit or 32- bit parallel interface to transmit and receive PCI Express data
- Allows integration of high speed components into a single functional block as seen by the endpoint device designer.
HSIC PHY
- Consumes <90mW during data transfer
- Consumes <50uW when not transferring data
- Uses standard chip digital and IO supplies
- Low pin count