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USB2.0 PHY & Controller

Overview

The INNO USB 2.0 PHY conforms to the specification of UTMI+ level 3 Revision 1.0 (USB 2.0 Transceiver Macrocell Interface Plus) and has excellent performance. As an integrated high-speed mixed signal circuit, the INNO USB 2.0 PHY supports not only the Low Speed (LS) traffic at 1.5Mbps and Full Speed (FS) traffic at 12Mbps, but also the High Speed (HS) traffic at 480Mbps, while retaining backward compatibility with USB1.1 legacy protocol.
The INNO USB 2.0 PHY is capable to handle the low-level protocol and signaling. In transmitting mode, the PHY serializes data, performs bit stuffing following NRZI encoding when needed, and then generates SYNC and EOP fields. Likewise, in receiving mode, it recovers clock from incoming data, strips the SYNC and EOP fields, performs NRZI decoding with bit un-stuffing when needed and then de-serializes the data. It supports17 modes of operations, including LS, FS, HS, and Device and Host.
The INNO USB 2.0 PHY can be pre-configured as a 30MHz 16-bit or 60MHz 8-bit UTMI data interface, which provides a complete on-chip transceiver physical solution with ESD protection.

Key Features

  • Compliant with USB Specification Revision 2.0, 1.1
  • Configurable 8-bit or 16-bit UTMI interface compliant with UTMI+ Specification Level 3 Revision 1.0
  • Supports 480Mbps (HS), 12Mbps (FS) and 1.5Mbps (LS) serial data transmission
  • Supports low latency hub mode with 40-bit time round trip delay
  • Supports all test modes as defined in the USB Specification Revision 2.0
  • Supports scan and loop-back BIST mode
  • Built-in I/O and ESD structure
  • On-die self-calibrated HS/FS/LS termination
  • Supports 12/19.2/20/24MHz (as long as the value is an aliquot part of 480) external crystal or on-chip reference clock with integrated phase-locked loop (PLL) oscillator

Deliverables

  • Databook and detailed physical implementation guides for the complete PHY
  • Library Exchange Format (LEF) file with pin size and locations
  • Gate-level netlist and Standard Delay Format (SDF) Timing file
  • Encrypted Verilog Models
  • Layout Versus Schematic (LVS) flattened netlist and report
  • Design Rule Check (DRC) report
  • GDSII database for foundry merge
  • Optional Test-chip and FPGA support
  • Optional backend integration

Technical Specifications

Foundry, Node
GF 55/28/22/14/12nm, HLMC 55/40/28nm, SMIC 55/40/28/14nm, Samsung 28/14/5/4nm, TSMC 55/40/28/22/16/12/6/5/4/3nm, UMC 55/40/28/22nm
Maturity
SP or MP or DR
GLOBALFOUNDRIES
In Production: 12nm , 14nm LPP , 22nm FDX , 28nm SLP , 55nm LPX
Silicon Proven: 12nm , 14nm LPP , 22nm FDX , 28nm SLP , 55nm LPX
SMIC
In Production: 14nm , 28nm HKC+ , 40nm LL , 55nm LL
Silicon Proven: 14nm , 28nm HKC+ , 40nm LL , 55nm LL
Samsung
In Production: 4nm , 5nm , 14nm , 28nm FDS , 28nm LPP
Silicon Proven: 4nm , 5nm , 14nm , 28nm FDS , 28nm LPP
TSMC
In Production: 3nm , 4nm , 5nm , 6nm , 12nm , 16nm , 22nm , 28nm HPC , 28nm HPCP , 28nm HPM , 40nm G , 40nm LP , 55nm LP
Silicon Proven: 3nm , 4nm , 5nm , 6nm , 12nm , 16nm , 22nm , 28nm HPC , 28nm HPCP , 28nm HPM , 40nm G , 40nm LP , 55nm LP
UMC
In Production: 22nm , 28nm , 28nm HPC , 40nm LP , 55nm
Silicon Proven: 22nm , 28nm HPC , 40nm LP , 55nm
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