PCI IP for GLOBALFOUNDRIES

Compare 11 PCI IP for GLOBALFOUNDRIES from 3 vendors (1 - 10)

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12nm

PHY for PCIe 3.1
- Supports PCIe 3.1, USB 3.1, DP-TX v1.4/eDP-TX v1.4b, SATA 3, 10G-KR and QSMII/SGMII
- Multi-protocol support for simultaneous independent links
- Supports SRIS and internal SSC generation
- Supports PCIe L1 sub-states
- Automatic calibration of on-chip termination resistors
- Supports internal and external clock sources with clock active detection
PCIe 2.0 PHY, GF 12LP+ x2 North/South (vertical) poly orientation
- Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- PCIe L1 substate power management
- Supports power gating and power island
PCIe 2.0 PHY, GF 12LP+ x1, North/South (vertical) poly orientation
- Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- PCIe L1 substate power management
- Supports power gating and power island
PCIe 2.0 PHY, GF 12LP x2, North/South (vertical) poly orientation
- Compliant with the PCI Express (PCIe®) 2.1 and PIPE specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- PCIe L1 substate power management
- Supports power gating and power island
PCIe 5.0 PHY, GF 12LP+ x1, North/South (vertical) poly orientation
- Supports all required features of the PCIe® 5.0, 4.0, 3.1, 2.1, 1.1, PIPE, and CXL 1.0, 1.1, and 2.0 specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE) supporting more than 36dB channel loss
- Adaptive receiver equalizer with programmable settings
PCIe 4.0 PHY in GF (14nm, 12nm)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Support PCIe 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
- Lane margining at the receiver
- Spread-spectrum clocking (SRIS)
PCIe 2.0 PHY in GF (40nm, 28nm, 22nm, 12nm)
- Physical coding sublayer (PCS) block with PIPE interface
- Supports PCIe power management features, including L1 substate
- Power gating for lowest standby power
- Low active power using voltage mode TX with under drive supply options
PCIe4/3/2/1 PHY & Controller
- Reference Clock:
- Internal PLL:
- Data Transmit:
- Data Receive:
SGMII PHY
- General:
- Interface:
- PMA-TX:
- PMA-RX:
PCIe5.0 PHY & Controller
- Fully compliant with PCI Express Base Specification Revision 5.0
- Fully compliant with PIPE Specifications Revision 4.4.1
- Support Root Complex and Endpoint Mode
- Support Gen1 (2.5Gbps), Gen2 (5Gbps), Gen3 (8Gbps), Gen4 (16Gbps), Gen5 (32Gbps)