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I2C IP for GLOBALFOUNDRIES

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Compare 19 I2C IP for GLOBALFOUNDRIES from 3 vendors (1 - 10)
  • I2C Controller IP- Master / Slave, Parameterized FIFO, Avalon Bus
    • The DB-I2C-MS-AVLN Controller IP Core interfaces a microprocessor via the Avalon Bus to an I2C Bus in Standard-Mode (100 Kbit/s) / Fast-Mode (400 Kbit/s) / Fast-Mode Plus (1 Mbit/s) / Hs-Mode (3.4+ Mb/s) / Ultra Fast-Mode (5 mbit/s).
    • The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.
    • The DB-I2C-MS-AVLN is a Master / Slave I2C Controller that in Master Mode controls the Transmit or Receive of data to or from slave I2C devices while in Slave Mode allows an external I2C Master device to control the Transmit or Receive of data.
    Block Diagram -- I2C Controller IP- Master / Slave, Parameterized FIFO, Avalon Bus
  • I2C Controller IP- Master / Slave, Parameterized FIFO, APB Bus

    • The Digital Blocks DB-I2C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I2C Bus in Standard-Mode (100 Kbit/s) / Fast-Mode (400 Kbit/s) / Fast-Mode Plus (1 Mbit/s) / Hs-Mode (3.4+ Mb/s) / Ultra Fast-Mode (5 mbit/s).

      The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.

      The DB-I2C-MS-APB is a Master/Slave I2C Controller that in Master Mode controls the Transmit or Receive of data to or from slave I2C devices while in Slave Mode allows an external I2C Master device to control the Transmit or Receive of data.

    Block Diagram -- I2C Controller IP- Master / Slave, Parameterized FIFO, APB Bus
  • I2C Controller IP- Master / Slave, Parameterized FIFO, AHB Bus

    • The DB-I2C-MS-AHB Controller IP Core interfaces a microprocessor via the AMBA AHB Bus to an I2C Bus in Standard-Mode (100 Kbit/s) / Fast-Mode (400 Kbit/s) / Fast-Mode Plus (1 Mbit/s) / Hs-Mode (3.4+ Mb/s) / Ultra Fast-Mode (5 mbit/s).

      The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.

      The DB-I2C-MS-AHB is a Master / Slave I2C Controller that in Master Mode controls the Transmit or Receive of data to or from slave I2C devices while in Slave Mode allows an external I2C Master device to control the Transmit or Receive of data.

    Block Diagram -- I2C Controller IP- Master / Slave, Parameterized FIFO, AHB Bus
  • I2C Controller IP- Master / Slave, Parameterized FIFO, AXI Bus
    • The DB-I2C-MS-AXI Controller IP Core interfaces a microprocessor via the AMBA AXI Bus to an I2C Bus in Standard-Mode (100 Kbit/s) / Fast-Mode (400 Kbit/s) / Fast-Mode Plus (1 Mbit/s) / Hs-Mode (3.4+ Mb/s) / Ultra Fast-Mode (5 mbit/s).
    • The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.
    • The DB-I2C-MS-AXI is a Master / Slave I2C Controller that in Master Mode controls the Transmit or Receive of data to or from slave I2C devices while in Slave Mode allows an external I2C Master device to control the Transmit or Receive of data.
    Block Diagram -- I2C Controller IP- Master / Slave, Parameterized FIFO, AXI Bus
  • I2C Controller IP – Master, Parameterized FIFO, AXI Bus
    • The DB-I2C-M-AXI Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2.0 AXI System Interconnect Fabric to an I2C Bus. The I2C is a two-wire bidirectional interface standard (SCL is Clock, SDA is Data) for transfer of bytes of information between two or more compliant I2C devices, typically with a microprocessor behind the master controller and one or more slave devices.
    • The DB-I2C-M-AXI is a Master I2C Controller that controls the Transmit or Receive of data to or from slave I2C devices. Figure 1 depicts the system view of the DB-I2C-M AXI Controller IP Core embedded within an integrated circuit device.
    Block Diagram -- I2C Controller IP – Master, Parameterized FIFO, AXI Bus
  • High voltage tolerant I/O
    • Scalable robustness
    • Area efficient
    • low capacitance option
  • 1.8V/3.3V I2C in GF (12nm)
    • Input Schmitt trigger
    • Compliance with I2C-bus specification and User Manual–April4, 2014, with I2C operating modes
    • Filter of 50 ns for Spike rejection
    • Automotive G1/G2 supported, ASIL-B certified
  • 1.8V/3.3V I2C 5V Failsafe Failtolerant Automotive Grade 1 in GF (12nm)
    • Input Schmitt trigger
    • Compliance with I2C-bus specification and User Manual–April4, 2014, with I2C operating modes
    • Filter of 50 ns for Spike rejection
    • Automotive G1/G2 supported, ASIL-B certified
  • IO I2C 3.3V in GF (22nm)
    • Input Schmitt trigger
    • Compliance with I2C-bus specification and User Manual–April4, 2014, with I2C operating modes
    • Filter of 50 ns for Spike rejection
    • Automotive G1/G2 supported, ASIL-B certified
  • 1.8V/3.3V I2C 5V Failsafe Failtolerant Automotive Grade 1 in GF (22nm)
    • Input Schmitt trigger
    • Compliance with I2C-bus specification and User Manual–April4, 2014, with I2C operating modes
    • Filter of 50 ns for Spike rejection
    • Automotive G1/G2 supported, ASIL-B certified
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