SMBus Verification IP

Overview

SMBus Verification IP provides an smart way to verify the SMBus bi-directional two-wire bus. The SmartDV's SMBus Verification IP is fully compliant with version 3.1 of the SMBus Specifications and provides the following features.

SMBus Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

SMBus Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports SMBus specification version 3.1.
Full SMBus Master and Slave functionality.
Supports all the SMBus commands as per the specs.
Supports programmable clock frequency of operation.
Support ARP command generation and response.
Support Timeout detection and generation.
Bus-accurate timing.
Packet Error Checking support.
Supports master/slave arbitration and clock synchronization.
Glitch insertion and detection.
Callbacks in master, slave and monitor for user processing of data.
Supports scoreboard checking.
Supports insertion of errors
- Master abort in middle of transaction.
- ACK on last read phase by master.
- Master continues on NACK after write NACK from slave.
- Random and Periodic clock period stretching by slave.
- Random Write NACK insertion by slave.
- PEC Error.
- Timeout error insertion.
- ACK for PEC field by master for read data
- Wrong ARP Address
- Unsupported command codes
- Illegal command lengths
Built-in monitors for protocol checking, including a global bus monitor.
Functional coverage to cover all functionality of SMBUS slave and master.
Support for multiple instantiations to create complex verification environment.
Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
SMBus Verification IP comes with complete testsuite to test every feature of SMBus specification.

Benefits

Faster testbench development and more complete verification of SMBus designs.
Easy to use command interface simplifies testbench control and configuration of Master and Slave.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the SMBus testcases to certify SMBus Master/Slave device.
Examples showing how to connect various components, and usage of BFM and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

Request Info