2.5GBase-KX/5GBase-KR/2.5GBase-T/5GBase-T Verification IP

Overview

The 2.5GBase-KX/5GBase-KR/2.5GBase-T/5GBase-T Ethernet Verification IP is compliant with IEEE 802.3cb specifications and verifies MAC-to-PHY layer interfaces of designs with a Ethernet interface 2.5GBase-KX/5GBase-KR/2.5GBase-T/5GBase-T. It can work with SystemVerilog, Vera, SystemC, E and Verilog HDL environment. 2.5GBase-KX/5GBase-KR/2.5GBase-T/5GBase-T verification IP is developed by experts in Ethernet, who have developed ethernet products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a ethernet product.

2.5GBase-KX/5GBase-KR/2.5GBase-T/5GBase-T Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

2.5GBase-KX/5GBase-KR/2.5GBase-T/5GBase-T Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Follows 2.5GBase-KX/5GBase-KR/2.5GBase-T/5GBase-T specification as defined in IEEE 802.3cb
Supports scrambler
Supports backplane auto-negotation
Supports CDR for serial protocols
Supports MDIO slave and master model as per Clause 22 and Clause 45
Supports Glitch insertion and detection
Supports all types of 2.5GBase-KX/5GBase-KR/2.5GBase-T/5GBase-T TX and RX errors insertion/detection.

Oversize, undersize, inrange, out of range Packet size errors
Missing SPD/EPD/SFD framing errors
SFD on wrong lane
CRC Error
Lane skew insertion
Disparity error injection
Invalid /D/ and /K/ character injection
Variable preamble and IPG insertion
Invalid block code insertion
Sync bit corruption
Scrambler error injection

2.5GBase-KX/5GBase-KR/2.5GBase-T/5GBase-T Verification IP comes with complete UNH Test suite
Comes with 2.5GBase-KX/5GBase-KR/2.5GBase-T/5GBase-T Tx BFM,2.5GBase-KX/5GBase-KR/2.5GBase-T/5GBase-T Rx BFM, and 2.5GBase-KX/5GBase-KR/2.5GBase-T/5GBase-T PCS Monitor
Monitor supports detection of all protocol violations.
Supports Pause frame generation and detection.
Built in coverage analysis.

Benefits

Faster testbench development and more complete verification of 2.5GBase-KX/5GBase-KR/2.5GBase-T/5GBase-T designs.
Easy to use command interface simplifies testbench control and configuration of 2.5GBase-KX/5GBase-KR/2.5GBase-T/5GBase-T TX and RX.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the testcases.
Examples showing how to connect various components, and usage of TXRX BFM and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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